board/amcc/sequoia/sdram.c

   1 /*
   2  * (C) Copyright 2006
   3  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   4  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   5  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   6  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   7  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
   8  *
   9  * (C) Copyright 2006-2007
  10  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 /* define DEBUG for debug output */
  29 #undef DEBUG
  30
  31 #include <common.h>
  32 #include <asm/processor.h>
  33 #include <asm/io.h>
  34 #include <ppc440.h>
  35
  36 /*-----------------------------------------------------------------------------+
  37  * Prototypes
  38  *-----------------------------------------------------------------------------*/
  39 extern int denali_wait_for_dlllock(void);
  40 extern void denali_core_search_data_eye(void);
  41
  42 #if defined(CONFIG_NAND_SPL)
  43 /* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
  44  * for the 4k NAND boot image so define bus_frequency to 133MHz here
  45  * which is save for the refresh counter setup.
  46  */
  47 #define get_bus_freq(val)       133000000
  48 #endif
  49
  50 /*************************************************************************
  51  *
  52  * initdram -- 440EPx's DDR controller is a DENALI Core
  53  *
  54  ************************************************************************/
  55 phys_size_t initdram (int board_type)
  56 {
  57 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  58 #if !defined(CONFIG_NAND_SPL)
  59         ulong speed = get_bus_freq(0);
  60 #else
  61         ulong speed = 133333333;        /* 133MHz is on the safe side   */
  62 #endif
  63
  64         mtsdram(DDR0_02, 0x00000000);
  65
  66         mtsdram(DDR0_00, 0x0000190A);
  67         mtsdram(DDR0_01, 0x01000000);
  68         mtsdram(DDR0_03, 0x02030602);
  69         mtsdram(DDR0_04, 0x0A020200);
  70         mtsdram(DDR0_05, 0x02020308);
  71         mtsdram(DDR0_06, 0x0102C812);
  72         mtsdram(DDR0_07, 0x000D0100);
  73         mtsdram(DDR0_08, 0x02430001);
  74         mtsdram(DDR0_09, 0x00011D5F);
  75         mtsdram(DDR0_10, 0x00000300);
  76         mtsdram(DDR0_11, 0x0027C800);
  77         mtsdram(DDR0_12, 0x00000003);
  78         mtsdram(DDR0_14, 0x00000000);
  79         mtsdram(DDR0_17, 0x19000000);
  80         mtsdram(DDR0_18, 0x19191919);
  81         mtsdram(DDR0_19, 0x19191919);
  82         mtsdram(DDR0_20, 0x0B0B0B0B);
  83         mtsdram(DDR0_21, 0x0B0B0B0B);
  84         mtsdram(DDR0_22, 0x00267F0B);
  85         mtsdram(DDR0_23, 0x00000000);
  86         mtsdram(DDR0_24, 0x01010002);
  87         if (speed > 133333334)
  88                 mtsdram(DDR0_26, 0x5B26050C);
  89         else
  90                 mtsdram(DDR0_26, 0x5B260408);
  91         mtsdram(DDR0_27, 0x0000682B);
  92         mtsdram(DDR0_28, 0x00000000);
  93         mtsdram(DDR0_31, 0x00000000);
  94         mtsdram(DDR0_42, 0x01000006);
  95         mtsdram(DDR0_43, 0x030A0200);
  96         mtsdram(DDR0_44, 0x00000003);
  97         mtsdram(DDR0_02, 0x00000001);
  98
  99         denali_wait_for_dlllock();
 100 #endif /* #ifndef CONFIG_NAND_U_BOOT */
 101
 102 #ifdef CONFIG_DDR_DATA_EYE
 103         /* -----------------------------------------------------------+
 104          * Perform data eye search if requested.
 105          * ----------------------------------------------------------*/
 106         denali_core_search_data_eye();
 107 #endif
 108
 109         /*
 110          * Clear possible errors resulting from data-eye-search.
 111          * If not done, then we could get an interrupt later on when
 112          * exceptions are enabled.
 113          */
 114         set_mcsr(get_mcsr());
 115
 116         return (CONFIG_SYS_MBYTES_SDRAM << 20);
 117 }