3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR
;
32 extern flash_info_t flash_info
[CFG_MAX_FLASH_BANKS
]; /* info for FLASH chips */
34 ulong
flash_get_size (ulong base
, int banknum
);
36 int board_early_init_f(void)
39 u32 sdr0_pfc1
, sdr0_pfc2
;
42 mtdcr(ebccfga
, xbcfg
);
43 mtdcr(ebccfgd
, 0xb8400000);
45 /*--------------------------------------------------------------------
47 *-------------------------------------------------------------------*/
48 /* test-only: take GPIO init from pcs440ep ???? in config file */
49 out32(GPIO0_OR
, 0x00000000);
50 out32(GPIO0_TCR
, 0x0000000f);
51 out32(GPIO0_OSRL
, 0x50015400);
52 out32(GPIO0_OSRH
, 0x550050aa);
53 out32(GPIO0_TSRL
, 0x50015400);
54 out32(GPIO0_TSRH
, 0x55005000);
55 out32(GPIO0_ISR1L
, 0x50000000);
56 out32(GPIO0_ISR1H
, 0x00000000);
57 out32(GPIO0_ISR2L
, 0x00000000);
58 out32(GPIO0_ISR2H
, 0x00000100);
59 out32(GPIO0_ISR3L
, 0x00000000);
60 out32(GPIO0_ISR3H
, 0x00000000);
62 out32(GPIO1_OR
, 0x00000000);
63 out32(GPIO1_TCR
, 0xc2000000);
64 out32(GPIO1_OSRL
, 0x5c280000);
65 out32(GPIO1_OSRH
, 0x00000000);
66 out32(GPIO1_TSRL
, 0x0c000000);
67 out32(GPIO1_TSRH
, 0x00000000);
68 out32(GPIO1_ISR1L
, 0x00005550);
69 out32(GPIO1_ISR1H
, 0x00000000);
70 out32(GPIO1_ISR2L
, 0x00050000);
71 out32(GPIO1_ISR2H
, 0x00000000);
72 out32(GPIO1_ISR3L
, 0x01400000);
73 out32(GPIO1_ISR3H
, 0x00000000);
75 /*--------------------------------------------------------------------
76 * Setup the interrupt controller polarities, triggers, etc.
77 *-------------------------------------------------------------------*/
78 mtdcr(uic0sr
, 0xffffffff); /* clear all */
79 mtdcr(uic0er
, 0x00000000); /* disable all */
80 mtdcr(uic0cr
, 0x00000005); /* ATI & UIC1 crit are critical */
81 mtdcr(uic0pr
, 0xfffff7ff); /* per ref-board manual */
82 mtdcr(uic0tr
, 0x00000000); /* per ref-board manual */
83 mtdcr(uic0vr
, 0x00000000); /* int31 highest, base=0x000 */
84 mtdcr(uic0sr
, 0xffffffff); /* clear all */
86 mtdcr(uic1sr
, 0xffffffff); /* clear all */
87 mtdcr(uic1er
, 0x00000000); /* disable all */
88 mtdcr(uic1cr
, 0x00000000); /* all non-critical */
89 mtdcr(uic1pr
, 0xffffffff); /* per ref-board manual */
90 mtdcr(uic1tr
, 0x00000000); /* per ref-board manual */
91 mtdcr(uic1vr
, 0x00000000); /* int31 highest, base=0x000 */
92 mtdcr(uic1sr
, 0xffffffff); /* clear all */
94 mtdcr(uic2sr
, 0xffffffff); /* clear all */
95 mtdcr(uic2er
, 0x00000000); /* disable all */
96 mtdcr(uic2cr
, 0x00000000); /* all non-critical */
97 mtdcr(uic2pr
, 0xffffffff); /* per ref-board manual */
98 mtdcr(uic2tr
, 0x00000000); /* per ref-board manual */
99 mtdcr(uic2vr
, 0x00000000); /* int31 highest, base=0x000 */
100 mtdcr(uic2sr
, 0xffffffff); /* clear all */
103 *(unsigned char *)(CFG_BCSR_BASE
| 0x04) = 0x00;
105 /* clear write protects */
106 *(unsigned char *)(CFG_BCSR_BASE
| 0x07) = 0x00;
108 /* enable Ethernet */
109 *(unsigned char *)(CFG_BCSR_BASE
| 0x08) = 0x00;
111 /* enable USB device */
112 *(unsigned char *)(CFG_BCSR_BASE
| 0x09) = 0x20;
114 /* select Ethernet pins */
115 mfsdr(SDR0_PFC1
, sdr0_pfc1
);
116 sdr0_pfc1
= (sdr0_pfc1
& ~SDR0_PFC1_SELECT_MASK
) | SDR0_PFC1_SELECT_CONFIG_4
;
117 mfsdr(SDR0_PFC2
, sdr0_pfc2
);
118 sdr0_pfc2
= (sdr0_pfc2
& ~SDR0_PFC2_SELECT_MASK
) | SDR0_PFC2_SELECT_CONFIG_4
;
119 mtsdr(SDR0_PFC2
, sdr0_pfc2
);
120 mtsdr(SDR0_PFC1
, sdr0_pfc1
);
122 /* PCI arbiter enabled */
123 mfsdr(sdr_pci0
, reg
);
124 mtsdr(sdr_pci0
, 0x80000000 | reg
);
126 /* setup NAND FLASH */
127 mfsdr(SDR0_CUST0
, sdr0_cust0
);
128 sdr0_cust0
= SDR0_CUST0_MUX_NDFC_SEL
|
129 SDR0_CUST0_NDFC_ENABLE
|
130 SDR0_CUST0_NDFC_BW_8_BIT
|
131 SDR0_CUST0_NDFC_ARE_MASK
|
132 (0x80000000 >> (28 + CFG_NAND_CS
));
133 mtsdr(SDR0_CUST0
, sdr0_cust0
);
138 /*---------------------------------------------------------------------------+
140 +---------------------------------------------------------------------------*/
141 int misc_init_r(void)
147 unsigned long usb2d0cr
= 0;
148 unsigned long usb2phy0cr
, usb2h0cr
= 0;
149 unsigned long sdr0_pfc1
;
150 char *act
= getenv("usbact");
157 /* Re-do sizing to get full correct info */
159 /* adjust flash start and offset */
160 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
161 gd
->bd
->bi_flashoffset
= 0;
163 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
164 mtdcr(ebccfga
, pb3cr
);
166 mtdcr(ebccfga
, pb0cr
);
168 pbcr
= mfdcr(ebccfgd
);
169 switch (gd
->bd
->bi_flashsize
) {
195 pbcr
= (pbcr
& 0x0001ffff) | gd
->bd
->bi_flashstart
| (size_val
<< 17);
196 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
197 mtdcr(ebccfga
, pb3cr
);
199 mtdcr(ebccfga
, pb0cr
);
201 mtdcr(ebccfgd
, pbcr
);
204 * Re-check to get correct base address
206 flash_get_size(gd
->bd
->bi_flashstart
, 0);
208 #ifdef CFG_ENV_IS_IN_FLASH
209 /* Monitor protection ON by default */
210 (void)flash_protect(FLAG_PROTECT_SET
,
215 /* Env protection ON by default */
216 (void)flash_protect(FLAG_PROTECT_SET
,
218 CFG_ENV_ADDR_REDUND
+ 2*CFG_ENV_SECT_SIZE
- 1,
226 if (act
== NULL
|| strcmp(act
, "hostdev") == 0) {
228 mfsdr(SDR0_PFC1
, sdr0_pfc1
);
229 mfsdr(SDR0_USB0
, usb2d0cr
);
230 mfsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
231 mfsdr(SDR0_USB2H0CR
, usb2h0cr
);
233 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_XOCLK_MASK
;
234 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_XOCLK_EXTERNAL
; /*0*/
235 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_WDINT_MASK
;
236 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ
; /*1*/
237 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DVBUS_MASK
;
238 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DVBUS_PURDIS
; /*0*/
239 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DWNSTR_MASK
;
240 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DWNSTR_HOST
; /*1*/
241 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_UTMICN_MASK
;
242 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_UTMICN_HOST
; /*1*/
244 /* An 8-bit/60MHz interface is the only possible alternative
245 when connecting the Device to the PHY */
246 usb2h0cr
= usb2h0cr
&~SDR0_USB2H0CR_WDINT_MASK
;
247 usb2h0cr
= usb2h0cr
| SDR0_USB2H0CR_WDINT_16BIT_30MHZ
; /*1*/
249 /* To enable the USB 2.0 Device function through the UTMI interface */
250 usb2d0cr
= usb2d0cr
&~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK
;
251 usb2d0cr
= usb2d0cr
| SDR0_USB2D0CR_USB2DEV_SELECTION
; /*1*/
253 sdr0_pfc1
= sdr0_pfc1
&~SDR0_PFC1_UES_MASK
;
254 sdr0_pfc1
= sdr0_pfc1
| SDR0_PFC1_UES_USB2D_SEL
; /*0*/
256 mtsdr(SDR0_PFC1
, sdr0_pfc1
);
257 mtsdr(SDR0_USB0
, usb2d0cr
);
258 mtsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
259 mtsdr(SDR0_USB2H0CR
, usb2h0cr
);
263 mtsdr(SDR0_SRST1
, 0x00000000);
265 mtsdr(SDR0_SRST0
, 0x00000000);
267 printf("USB: Host(int phy) Device(ext phy)\n");
269 } else if (strcmp(act
, "dev") == 0) {
270 /*-------------------PATCH-------------------------------*/
271 mfsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
273 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_XOCLK_MASK
;
274 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_XOCLK_EXTERNAL
; /*0*/
275 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DVBUS_MASK
;
276 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DVBUS_PURDIS
; /*0*/
277 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DWNSTR_MASK
;
278 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DWNSTR_HOST
; /*1*/
279 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_UTMICN_MASK
;
280 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_UTMICN_HOST
; /*1*/
281 mtsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
284 mtsdr(SDR0_SRST1
, 0x672c6000);
287 mtsdr(SDR0_SRST0
, 0x00000080);
290 mtsdr(SDR0_SRST1
, 0x60206000);
292 *(unsigned int *)(0xe0000350) = 0x00000001;
295 mtsdr(SDR0_SRST1
, 0x60306000);
296 /*-------------------PATCH-------------------------------*/
299 mfsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
300 mfsdr(SDR0_USB2H0CR
, usb2h0cr
);
301 mfsdr(SDR0_USB0
, usb2d0cr
);
302 mfsdr(SDR0_PFC1
, sdr0_pfc1
);
304 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_XOCLK_MASK
;
305 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_XOCLK_EXTERNAL
; /*0*/
306 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_WDINT_MASK
;
307 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ
; /*0*/
308 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DVBUS_MASK
;
309 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DVBUS_PUREN
; /*1*/
310 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DWNSTR_MASK
;
311 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DWNSTR_DEV
; /*0*/
312 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_UTMICN_MASK
;
313 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_UTMICN_DEV
; /*0*/
315 usb2h0cr
= usb2h0cr
&~SDR0_USB2H0CR_WDINT_MASK
;
316 usb2h0cr
= usb2h0cr
| SDR0_USB2H0CR_WDINT_8BIT_60MHZ
; /*0*/
318 usb2d0cr
= usb2d0cr
&~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK
;
319 usb2d0cr
= usb2d0cr
| SDR0_USB2D0CR_EBC_SELECTION
; /*0*/
321 sdr0_pfc1
= sdr0_pfc1
&~SDR0_PFC1_UES_MASK
;
322 sdr0_pfc1
= sdr0_pfc1
| SDR0_PFC1_UES_EBCHR_SEL
; /*1*/
324 mtsdr(SDR0_USB2H0CR
, usb2h0cr
);
325 mtsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
326 mtsdr(SDR0_USB0
, usb2d0cr
);
327 mtsdr(SDR0_PFC1
, sdr0_pfc1
);
331 mtsdr(SDR0_SRST1
, 0x00000000);
333 mtsdr(SDR0_SRST0
, 0x00000000);
335 printf("USB: Device(int phy)\n");
337 #endif /* CONFIG_440EPX */
340 * Clear PLB4A0_ACR[WRP]
341 * This fix will make the MAL burst disabling patch for the Linux
342 * EMAC driver obsolete.
344 reg
= mfdcr(plb4_acr
) & ~PLB4_ACR_WRP
;
345 mtdcr(plb4_acr
, reg
);
352 char *s
= getenv("serial#");
355 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
357 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
368 #if defined(CFG_DRAM_TEST)
371 unsigned long *mem
= (unsigned long *)0;
372 const unsigned long kend
= (1024 / sizeof(unsigned long));
377 for (k
= 0; k
< CFG_MBYTES_SDRAM
;
378 ++k
, mem
+= (1024 / sizeof(unsigned long))) {
379 if ((k
& 1023) == 0) {
380 printf("%3d MB\r", k
/ 1024);
383 memset(mem
, 0xaaaaaaaa, 1024);
384 for (n
= 0; n
< kend
; ++n
) {
385 if (mem
[n
] != 0xaaaaaaaa) {
386 printf("SDRAM test fails at: %08x\n",
392 memset(mem
, 0x55555555, 1024);
393 for (n
= 0; n
< kend
; ++n
) {
394 if (mem
[n
] != 0x55555555) {
395 printf("SDRAM test fails at: %08x\n",
401 printf("SDRAM test passes\n");
406 /*************************************************************************
409 * This routine is called just prior to registering the hose and gives
410 * the board the opportunity to check things. Returning a value of zero
411 * indicates that things are bad & PCI initialization should be aborted.
413 * Different boards may wish to customize the pci controller structure
414 * (add regions, override default access routines, etc) or perform
415 * certain pre-initialization actions.
417 ************************************************************************/
418 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
419 int pci_pre_init(struct pci_controller
*hose
)
423 /*--------------------------------------------------------------------------+
424 * Cactus is always configured as the host & requires the
425 * PCI arbiter to be enabled ???
426 *--------------------------------------------------------------------------*/
428 mfsdr(sdr_sdstp1
, strap
);
429 if ((strap
& SDR0_SDSTP1_PAE_MASK
) == 0) {
430 printf("PCI: SDR0_STRP1[PAE] not set.\n");
431 printf("PCI: Configuration aborted.\n");
436 /*-------------------------------------------------------------------------+
437 | Set priority for all PLB3 devices to 0.
438 | Set PLB3 arbiter to fair mode.
439 +-------------------------------------------------------------------------*/
440 mfsdr(sdr_amp1
, addr
);
441 mtsdr(sdr_amp1
, (addr
& 0x000000FF) | 0x0000FF00);
442 addr
= mfdcr(plb3_acr
);
443 mtdcr(plb3_acr
, addr
| 0x80000000);
445 /*-------------------------------------------------------------------------+
446 | Set priority for all PLB4 devices to 0.
447 +-------------------------------------------------------------------------*/
448 mfsdr(sdr_amp0
, addr
);
449 mtsdr(sdr_amp0
, (addr
& 0x000000FF) | 0x0000FF00);
450 addr
= mfdcr(plb4_acr
) | 0xa0000000; /* Was 0x8---- */
451 mtdcr(plb4_acr
, addr
);
453 /*-------------------------------------------------------------------------+
454 | Set Nebula PLB4 arbiter to fair mode.
455 +-------------------------------------------------------------------------*/
457 addr
= (mfdcr(plb0_acr
) & ~plb0_acr_ppm_mask
) | plb0_acr_ppm_fair
;
458 addr
= (addr
& ~plb0_acr_hbu_mask
) | plb0_acr_hbu_enabled
;
459 addr
= (addr
& ~plb0_acr_rdp_mask
) | plb0_acr_rdp_4deep
;
460 addr
= (addr
& ~plb0_acr_wrp_mask
) | plb0_acr_wrp_2deep
;
461 mtdcr(plb0_acr
, addr
);
464 addr
= (mfdcr(plb1_acr
) & ~plb1_acr_ppm_mask
) | plb1_acr_ppm_fair
;
465 addr
= (addr
& ~plb1_acr_hbu_mask
) | plb1_acr_hbu_enabled
;
466 addr
= (addr
& ~plb1_acr_rdp_mask
) | plb1_acr_rdp_4deep
;
467 addr
= (addr
& ~plb1_acr_wrp_mask
) | plb1_acr_wrp_2deep
;
468 mtdcr(plb1_acr
, addr
);
472 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
474 /*************************************************************************
477 * The bootstrap configuration provides default settings for the pci
478 * inbound map (PIM). But the bootstrap config choices are limited and
479 * may not be sufficient for a given board.
481 ************************************************************************/
482 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
483 void pci_target_init(struct pci_controller
*hose
)
485 /*--------------------------------------------------------------------------+
486 * Set up Direct MMIO registers
487 *--------------------------------------------------------------------------*/
488 /*--------------------------------------------------------------------------+
489 | PowerPC440EPX PCI Master configuration.
490 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
491 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
492 | Use byte reversed out routines to handle endianess.
493 | Make this region non-prefetchable.
494 +--------------------------------------------------------------------------*/
495 out32r(PCIX0_PMM0MA
, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
496 out32r(PCIX0_PMM0LA
, CFG_PCI_MEMBASE
); /* PMM0 Local Address */
497 out32r(PCIX0_PMM0PCILA
, CFG_PCI_MEMBASE
); /* PMM0 PCI Low Address */
498 out32r(PCIX0_PMM0PCIHA
, 0x00000000); /* PMM0 PCI High Address */
499 out32r(PCIX0_PMM0MA
, 0xE0000001); /* 512M + No prefetching, and enable region */
501 out32r(PCIX0_PMM1MA
, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
502 out32r(PCIX0_PMM1LA
, CFG_PCI_MEMBASE2
); /* PMM0 Local Address */
503 out32r(PCIX0_PMM1PCILA
, CFG_PCI_MEMBASE2
); /* PMM0 PCI Low Address */
504 out32r(PCIX0_PMM1PCIHA
, 0x00000000); /* PMM0 PCI High Address */
505 out32r(PCIX0_PMM1MA
, 0xE0000001); /* 512M + No prefetching, and enable region */
507 out32r(PCIX0_PTM1MS
, 0x00000001); /* Memory Size/Attribute */
508 out32r(PCIX0_PTM1LA
, 0); /* Local Addr. Reg */
509 out32r(PCIX0_PTM2MS
, 0); /* Memory Size/Attribute */
510 out32r(PCIX0_PTM2LA
, 0); /* Local Addr. Reg */
512 /*--------------------------------------------------------------------------+
513 * Set up Configuration registers
514 *--------------------------------------------------------------------------*/
516 /* Program the board's subsystem id/vendor id */
517 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID
,
518 CFG_PCI_SUBSYS_VENDORID
);
519 pci_write_config_word(0, PCI_SUBSYSTEM_ID
, CFG_PCI_SUBSYS_ID
);
521 /* Configure command register as bus master */
522 pci_write_config_word(0, PCI_COMMAND
, PCI_COMMAND_MASTER
);
524 /* 240nS PCI clock */
525 pci_write_config_word(0, PCI_LATENCY_TIMER
, 1);
527 /* No error reporting */
528 pci_write_config_word(0, PCI_ERREN
, 0);
530 pci_write_config_dword(0, PCI_BRDGOPT2
, 0x00000101);
533 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
535 /*************************************************************************
538 ************************************************************************/
539 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
540 void pci_master_init(struct pci_controller
*hose
)
542 unsigned short temp_short
;
544 /*--------------------------------------------------------------------------+
545 | Write the PowerPC440 EP PCI Configuration regs.
546 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
547 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
548 +--------------------------------------------------------------------------*/
549 pci_read_config_word(0, PCI_COMMAND
, &temp_short
);
550 pci_write_config_word(0, PCI_COMMAND
,
551 temp_short
| PCI_COMMAND_MASTER
|
554 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
556 /*************************************************************************
559 * This routine is called to determine if a pci scan should be
560 * performed. With various hardware environments (especially cPCI and
561 * PPMC) it's insufficient to depend on the state of the arbiter enable
562 * bit in the strap register, or generic host/adapter assumptions.
564 * Rather than hard-code a bad assumption in the general 440 code, the
565 * 440 pci code requires the board to decide at runtime.
567 * Return 0 for adapter mode, non-zero for host (monarch) mode.
570 ************************************************************************/
571 #if defined(CONFIG_PCI)
572 int is_pci_host(struct pci_controller
*hose
)
574 /* Cactus is always configured as host. */
577 #endif /* defined(CONFIG_PCI) */