board/apollon/apollon.c

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Samsung Electronics.
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  *
   6  * Derived from omap2420
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26 #include <common.h>
  27 #include <asm/arch/omap2420.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/bits.h>
  30 #include <asm/arch/mux.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/arch/sys_info.h>
  33 #include <asm/arch/mem.h>
  34 #include <asm/mach-types.h>
  35
  36 void wait_for_command_complete(unsigned int wd_base);
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define write_config_reg(reg, value)                                    \
  41 do {                                                                    \
  42         writeb(value, reg);                                             \
  43 } while (0)
  44
  45 #define mask_config_reg(reg, mask)                                      \
  46 do {                                                                    \
  47         char value = readb(reg) & ~(mask);                              \
  48         writeb(value, reg);                                             \
  49 } while (0)
  50
  51 /*******************************************************
  52  * Routine: delay
  53  * Description: spinning delay to use before udelay works
  54  ******************************************************/
  55 static inline void delay(unsigned long loops)
  56 {
  57         __asm__("1:\n" "subs %0, %1, #1\n"
  58                   "bne 1b":"=r" (loops):"0"(loops));
  59 }
  60
  61 /*****************************************
  62  * Routine: board_init
  63  * Description: Early hardware init.
  64  *****************************************/
  65 int board_init(void)
  66 {
  67         gpmc_init();            /* in SRAM or SDRM, finish GPMC */
  68
  69         gd->bd->bi_arch_number = 919;
  70         /* adress of boot parameters */
  71         gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
  72
  73         return 0;
  74 }
  75
  76 /**********************************************************
  77  * Routine: s_init
  78  * Description: Does early system init of muxing and clocks.
  79  * - Called path is with sram stack.
  80  **********************************************************/
  81 void s_init(void)
  82 {
  83         watchdog_init();
  84         set_muxconf_regs();
  85         delay(100);
  86
  87         peripheral_enable();
  88         icache_enable();
  89 }
  90
  91 /*******************************************************
  92  * Routine: misc_init_r
  93  * Description: Init ethernet (done here so udelay works)
  94  ********************************************************/
  95 int misc_init_r(void)
  96 {
  97         ether_init();           /* better done here so timers are init'ed */
  98         return (0);
  99 }
 100
 101 /****************************************
 102  * Routine: watchdog_init
 103  * Description: Shut down watch dogs
 104  *****************************************/
 105 void watchdog_init(void)
 106 {
 107         /* There are 4 watch dogs.  1 secure, and 3 general purpose.
 108          * The ROM takes care of the secure one. Of the 3 GP ones,
 109          * 1 can reset us directly, the other 2 only generate MPU interrupts.
 110          */
 111         __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
 112         wait_for_command_complete(WD2_BASE);
 113         __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
 114
 115 #define MPU_WD_CLOCKED 1
 116 #if MPU_WD_CLOCKED
 117         /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
 118         __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
 119         wait_for_command_complete(WD3_BASE);
 120         __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
 121
 122         __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
 123         wait_for_command_complete(WD4_BASE);
 124         __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
 125 #endif
 126 }
 127
 128 /******************************************************
 129  * Routine: wait_for_command_complete
 130  * Description: Wait for posting to finish on watchdog
 131  ******************************************************/
 132 void wait_for_command_complete(unsigned int wd_base)
 133 {
 134         int pending = 1;
 135         do {
 136                 pending = __raw_readl(wd_base + WWPS);
 137         } while (pending);
 138 }
 139
 140 /*******************************************************************
 141  * Routine:ether_init
 142  * Description: take the Ethernet controller out of reset and wait
 143  *                 for the EEPROM load to complete.
 144  ******************************************************************/
 145 void ether_init(void)
 146 {
 147 #ifdef CONFIG_DRIVER_LAN91C96
 148         int cnt = 20;
 149
 150         __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
 151
 152         __raw_writew(0x0, LAN_RESET_REGISTER);
 153         do {
 154                 __raw_writew(0x1, LAN_RESET_REGISTER);
 155                 udelay(100);
 156                 if (cnt == 0) {
 157                         printf("1. eth reset err\n");
 158                         goto eth_reset_err_out;
 159                 }
 160                 --cnt;
 161         } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
 162
 163         cnt = 20;
 164
 165         do {
 166                 __raw_writew(0x0, LAN_RESET_REGISTER);
 167                 udelay(100);
 168                 if (cnt == 0) {
 169                         printf("2. eth reset err\n");
 170                         goto eth_reset_err_out;
 171                 }
 172                 --cnt;
 173         } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
 174         udelay(1000);
 175
 176         mask_config_reg(ETH_CONTROL_REG, 0x01);
 177         udelay(1000);
 178
 179 eth_reset_err_out:
 180         return;
 181 #endif
 182 }
 183
 184 /**********************************************
 185  * Routine: dram_init
 186  * Description: sets uboots idea of sdram size
 187  **********************************************/
 188 int dram_init(void)
 189 {
 190         unsigned int size0 = 0, size1 = 0;
 191         u32 mtype, btype, rev = 0, cpu = 0;
 192 #define NOT_EARLY 0
 193
 194         btype = get_board_type();
 195         mtype = get_mem_type();
 196         rev = get_cpu_rev();
 197         cpu = get_cpu_type();
 198
 199         display_board_info(btype);
 200
 201         if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
 202                 /* init other chip select */
 203                 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
 204         }
 205
 206         size0 = get_sdr_cs_size(SDRC_CS0_OSET);
 207         size1 = get_sdr_cs_size(SDRC_CS1_OSET);
 208
 209         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 210         gd->bd->bi_dram[0].size = size0;
 211 #if CONFIG_NR_DRAM_BANKS > 1
 212         gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
 213         gd->bd->bi_dram[1].size = size1;
 214 #endif
 215
 216         return 0;
 217 }
 218
 219 /**********************************************************
 220  * Routine: set_muxconf_regs
 221  * Description: Setting up the configuration Mux registers
 222  *              specific to the hardware
 223  *********************************************************/
 224 void set_muxconf_regs(void)
 225 {
 226         muxSetupSDRC();
 227         muxSetupGPMC();
 228         muxSetupUsb0();         /* USB Device */
 229         muxSetupUsbHost();      /* USB Host */
 230         muxSetupUART1();
 231         muxSetupLCD();
 232         muxSetupMMCSD();
 233         muxSetupTouchScreen();
 234 }
 235
 236 /*****************************************************************
 237  * Routine: peripheral_enable
 238  * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 239  ******************************************************************/
 240 void peripheral_enable(void)
 241 {
 242         unsigned int v, if_clks = 0, func_clks = 0;
 243
 244         /* Enable GP2 timer. */
 245         if_clks |= BIT4 | BIT3;
 246         func_clks |= BIT4 | BIT3;
 247         /* Sys_clk input OMAP2420_GPT2 */
 248         v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
 249         __raw_writel(v, CM_CLKSEL2_CORE);
 250         __raw_writel(0x1, CM_CLKSEL_WKUP);
 251
 252 #ifdef CFG_NS16550
 253         /* Enable UART1 clock */
 254         func_clks |= BIT21;
 255         if_clks |= BIT21;
 256 #endif
 257         /* Interface clocks on */
 258         v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
 259         __raw_writel(v, CM_ICLKEN1_CORE);
 260         /* Functional Clocks on */
 261         v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
 262         __raw_writel(v, CM_FCLKEN1_CORE);
 263         delay(1000);
 264
 265 #ifndef KERNEL_UPDATED
 266         {
 267 #define V1 0xffffffff
 268 #define V2 0x00000007
 269
 270                 __raw_writel(V1, CM_FCLKEN1_CORE);
 271                 __raw_writel(V2, CM_FCLKEN2_CORE);
 272                 __raw_writel(V1, CM_ICLKEN1_CORE);
 273                 __raw_writel(V1, CM_ICLKEN2_CORE);
 274         }
 275 #endif
 276 }
 277
 278 /****************************************
 279  * Routine: muxSetupUsb0   (ostboot)
 280  * Description: Setup usb muxing
 281  *****************************************/
 282 void muxSetupUsb0(void)
 283 {
 284         mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
 285         mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
 286         mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
 287         mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
 288         mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
 289         mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
 290         mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
 291 }
 292
 293 /****************************************
 294  * Routine: muxSetupUSBHost   (ostboot)
 295  * Description: Setup USB Host muxing
 296  *****************************************/
 297 void muxSetupUsbHost(void)
 298 {
 299         /* V19 */
 300         write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
 301         /* W20 */
 302         write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
 303         /* N14 */
 304         write_config_reg(CONTROL_PADCONF_GPIO69, 3);
 305         /* P15 */
 306         write_config_reg(CONTROL_PADCONF_GPIO70, 3);
 307         /* L18 */
 308         write_config_reg(CONTROL_PADCONF_GPIO102, 3);
 309         /* L19 */
 310         write_config_reg(CONTROL_PADCONF_GPIO103, 3);
 311         /* K15 */
 312         write_config_reg(CONTROL_PADCONF_GPIO104, 3);
 313         /* K14 */
 314         write_config_reg(CONTROL_PADCONF_GPIO105, 3);
 315 }
 316
 317 /****************************************
 318  * Routine: muxSetupUART1  (ostboot)
 319  * Description: Set up uart1 muxing
 320  *****************************************/
 321 void muxSetupUART1(void)
 322 {
 323         /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
 324         write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
 325         /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
 326         write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
 327         /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
 328         write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
 329         /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
 330         write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
 331 }
 332
 333 /****************************************
 334  * Routine: muxSetupLCD   (ostboot)
 335  * Description: Setup lcd muxing
 336  *****************************************/
 337 void muxSetupLCD(void)
 338 {
 339         /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
 340         write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
 341         /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
 342         write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
 343         /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
 344         write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
 345         /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
 346         write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
 347         /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
 348         write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
 349         /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
 350         write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
 351         /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
 352         write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
 353         /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
 354         write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
 355         /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
 356         write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
 357         /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
 358         write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
 359         /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
 360         write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
 361         /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
 362         write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
 363         /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
 364         write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
 365         /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
 366         write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
 367         /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
 368         write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
 369         /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
 370         write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
 371         /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
 372         write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
 373         /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
 374         write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
 375         /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
 376         write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
 377         /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
 378         write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
 379         /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
 380         write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
 381         /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
 382         write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
 383 }
 384
 385 /****************************************
 386  * Routine: muxSetupMMCSD (ostboot)
 387  * Description: set up MMC muxing
 388  *****************************************/
 389 void muxSetupMMCSD(void)
 390 {
 391         /* SDMMC_CLKI pin configuration,  PIN = H15, Mode = 0, PUPD=Disabled */
 392         write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
 393         /* SDMMC_CLKO pin configuration,  PIN = G19, Mode = 0, PUPD=Disabled */
 394         write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
 395         /* SDMMC_CMD pin configuration,   PIN = H18, Mode = 0, PUPD=Disabled */
 396         write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
 397         /* SDMMC_DAT0 pin configuration,  PIN = F20, Mode = 0, PUPD=Disabled */
 398         write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
 399         /* SDMMC_DAT1 pin configuration,  PIN = H14, Mode = 0, PUPD=Disabled */
 400         write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
 401         /* SDMMC_DAT2 pin configuration,  PIN = E19, Mode = 0, PUPD=Disabled */
 402         write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
 403         /* SDMMC_DAT3 pin configuration,  PIN = D19, Mode = 0, PUPD=Disabled */
 404         write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
 405         /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
 406         write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
 407         /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
 408         write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
 409         /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
 410         write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
 411         /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
 412         write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
 413         /* SDMMC_CDIR pin configuration,  PIN = G18, Mode = 0, PUPD=Disabled */
 414         write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
 415 }
 416
 417 /******************************************
 418  * Routine: muxSetupTouchScreen (ostboot)
 419  * Description:  Set up touch screen muxing
 420  *******************************************/
 421 void muxSetupTouchScreen(void)
 422 {
 423         /* SPI1_CLK pin configuration,  PIN = U18, Mode = 0, PUPD=Disabled */
 424         write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
 425         /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
 426         write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
 427         /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
 428         write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
 429         /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
 430         write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
 431 #define CONTROL_PADCONF_GPIO85  CONTROL_PADCONF_SPI1_NCS1
 432         /* PEN_IRQ pin configuration,   PIN = N15, Mode = 3, PUPD=Disabled */
 433         write_config_reg(CONTROL_PADCONF_GPIO85, 3);
 434 }
 435
 436 /***************************************************************
 437  * Routine: muxSetupGPMC (ostboot)
 438  * Description: Configures balls which cam up in protected mode
 439  ***************************************************************/
 440 void muxSetupGPMC(void)
 441 {
 442         /* gpmc_io_dir, MCR */
 443         volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
 444         *MCR = 0x19000000;
 445
 446         /* NOR FLASH CS0 */
 447         /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
 448         write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
 449         /* MPDB(Multi Port Debug Port) CS1 */
 450         /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
 451         write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
 452         /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
 453         write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
 454         /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
 455         write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
 456         /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
 457         write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
 458         /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
 459         write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
 460         /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
 461         write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
 462         /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
 463         write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
 464 }
 465
 466 /****************************************************************
 467  * Routine: muxSetupSDRC  (ostboot)
 468  * Description: Configures balls which come up in protected mode
 469  ****************************************************************/
 470 void muxSetupSDRC(void)
 471 {
 472         /* It's set by IPL */
 473 }