board/atmel/at91sam9260ek/at91sam9260ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91sam9260.h>
  27 #include <asm/arch/at91sam9260_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_pmc.h>
  30 #include <asm/arch/at91_rstc.h>
  31 #include <asm/arch/gpio.h>
  32 #include <asm/arch/io.h>
  33 #include <asm/arch/hardware.h>
  34 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  35 #include <net.h>
  36 #endif
  37 #include <netdev.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 /* ------------------------------------------------------------------------- */
  42 /*
  43  * Miscelaneous platform dependent initialisations
  44  */
  45
  46 static void at91sam9260ek_serial_hw_init(void)
  47 {
  48 #ifdef CONFIG_USART0
  49         at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD0 */
  50         at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD0 */
  51         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
  52 #endif
  53
  54 #ifdef CONFIG_USART1
  55         at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD1 */
  56         at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD1 */
  57         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
  58 #endif
  59
  60 #ifdef CONFIG_USART2
  61         at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD2 */
  62         at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD2 */
  63         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
  64 #endif
  65
  66 #ifdef CONFIG_USART3    /* DBGU */
  67         at91_set_A_periph(AT91_PIN_PB14, 0);            /* DRXD */
  68         at91_set_A_periph(AT91_PIN_PB15, 1);            /* DTXD */
  69         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  70 #endif
  71 }
  72
  73 #ifdef CONFIG_CMD_NAND
  74 static void at91sam9260ek_nand_hw_init(void)
  75 {
  76         unsigned long csa;
  77
  78         /* Enable CS3 */
  79         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  80         at91_sys_write(AT91_MATRIX_EBICSA,
  81                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  82
  83         /* Configure SMC CS3 for NAND/SmartMedia */
  84         at91_sys_write(AT91_SMC_SETUP(3),
  85                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  86                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  87         at91_sys_write(AT91_SMC_PULSE(3),
  88                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  89                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  90         at91_sys_write(AT91_SMC_CYCLE(3),
  91                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  92         at91_sys_write(AT91_SMC_MODE(3),
  93                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  94                        AT91_SMC_EXNWMODE_DISABLE |
  95 #ifdef CONFIG_SYS_NAND_DBW_16
  96                        AT91_SMC_DBW_16 |
  97 #else /* CONFIG_SYS_NAND_DBW_8 */
  98                        AT91_SMC_DBW_8 |
  99 #endif
 100                        AT91_SMC_TDF_(2));
 101
 102         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
 103
 104         /* Configure RDY/BSY */
 105         at91_set_gpio_input(AT91_PIN_PC13, 1);
 106
 107         /* Enable NandFlash */
 108         at91_set_gpio_output(AT91_PIN_PC14, 1);
 109 }
 110 #endif
 111
 112 #ifdef CONFIG_HAS_DATAFLASH
 113 static void at91sam9260ek_spi_hw_init(void)
 114 {
 115         at91_set_A_periph(AT91_PIN_PA3, 0);     /* SPI0_NPCS0 */
 116         at91_set_B_periph(AT91_PIN_PC11, 0);    /* SPI0_NPCS1 */
 117
 118         at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 119         at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 120         at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 121
 122         /* Enable clock */
 123         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
 124 }
 125 #endif
 126
 127 #ifdef CONFIG_MACB
 128 static void at91sam9260ek_macb_hw_init(void)
 129 {
 130         /* Enable clock */
 131         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
 132
 133         /*
 134          * Disable pull-up on:
 135          *      RXDV (PA17) => PHY normal mode (not Test mode)
 136          *      ERX0 (PA14) => PHY ADDR0
 137          *      ERX1 (PA15) => PHY ADDR1
 138          *      ERX2 (PA25) => PHY ADDR2
 139          *      ERX3 (PA26) => PHY ADDR3
 140          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
 141          *
 142          * PHY has internal pull-down
 143          */
 144         writel(pin_to_mask(AT91_PIN_PA14) |
 145                pin_to_mask(AT91_PIN_PA15) |
 146                pin_to_mask(AT91_PIN_PA17) |
 147                pin_to_mask(AT91_PIN_PA25) |
 148                pin_to_mask(AT91_PIN_PA26) |
 149                pin_to_mask(AT91_PIN_PA28),
 150                pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 151
 152         /* Need to reset PHY -> 500ms reset */
 153         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 154                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
 155                                      AT91_RSTC_URSTEN);
 156
 157         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 158
 159         /* Wait for end hardware reset */
 160         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 161
 162         /* Restore NRST value */
 163         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 164                                      (AT91_RSTC_ERSTL & (0x0 << 8)) |
 165                                      AT91_RSTC_URSTEN);
 166
 167         /* Re-enable pull-up */
 168         writel(pin_to_mask(AT91_PIN_PA14) |
 169                pin_to_mask(AT91_PIN_PA15) |
 170                pin_to_mask(AT91_PIN_PA17) |
 171                pin_to_mask(AT91_PIN_PA25) |
 172                pin_to_mask(AT91_PIN_PA26) |
 173                pin_to_mask(AT91_PIN_PA28),
 174                pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 175
 176         at91_set_A_periph(AT91_PIN_PA19, 0);    /* ETXCK_EREFCK */
 177         at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
 178         at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERX0 */
 179         at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERX1 */
 180         at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERXER */
 181         at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXEN */
 182         at91_set_A_periph(AT91_PIN_PA12, 0);    /* ETX0 */
 183         at91_set_A_periph(AT91_PIN_PA13, 0);    /* ETX1 */
 184         at91_set_A_periph(AT91_PIN_PA21, 0);    /* EMDIO */
 185         at91_set_A_periph(AT91_PIN_PA20, 0);    /* EMDC */
 186
 187 #ifndef CONFIG_RMII
 188         at91_set_B_periph(AT91_PIN_PA28, 0);    /* ECRS */
 189         at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECOL */
 190         at91_set_B_periph(AT91_PIN_PA25, 0);    /* ERX2 */
 191         at91_set_B_periph(AT91_PIN_PA26, 0);    /* ERX3 */
 192         at91_set_B_periph(AT91_PIN_PA27, 0);    /* ERXCK */
 193 #if defined(CONFIG_AT91SAM9260EK)
 194         /*
 195          * use PA10, PA11 for ETX2, ETX3.
 196          * PA23 and PA24 are for TWI EEPROM
 197          */
 198         at91_set_B_periph(AT91_PIN_PA10, 0);    /* ETX2 */
 199         at91_set_B_periph(AT91_PIN_PA11, 0);    /* ETX3 */
 200 #else
 201         at91_set_B_periph(AT91_PIN_PA23, 0);    /* ETX2 */
 202         at91_set_B_periph(AT91_PIN_PA24, 0);    /* ETX3 */
 203 #endif
 204         at91_set_B_periph(AT91_PIN_PA22, 0);    /* ETXER */
 205 #endif
 206
 207 }
 208 #endif
 209
 210 int board_init(void)
 211 {
 212         /* Enable Ctrlc */
 213         console_init_f();
 214
 215         /* arch number of AT91SAM9260EK-Board */
 216         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
 217         /* adress of boot parameters */
 218         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 219
 220         at91sam9260ek_serial_hw_init();
 221 #ifdef CONFIG_CMD_NAND
 222         at91sam9260ek_nand_hw_init();
 223 #endif
 224 #ifdef CONFIG_HAS_DATAFLASH
 225         at91sam9260ek_spi_hw_init();
 226 #endif
 227 #ifdef CONFIG_MACB
 228         at91sam9260ek_macb_hw_init();
 229 #endif
 230
 231         return 0;
 232 }
 233
 234 int dram_init(void)
 235 {
 236         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 237         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 238         return 0;
 239 }
 240
 241 #ifdef CONFIG_RESET_PHY_R
 242 void reset_phy(void)
 243 {
 244 #ifdef CONFIG_MACB
 245         /*
 246          * Initialize ethernet HW addr prior to starting Linux,
 247          * needed for nfsroot
 248          */
 249         eth_init(gd->bd);
 250 #endif
 251 }
 252 #endif
 253
 254 int board_eth_init(bd_t *bis)
 255 {
 256         int rc = 0;
 257 #ifdef CONFIG_MACB
 258         rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
 259 #endif
 260         return rc;
 261 }