board/bc3450/bc3450.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2004-2005
   9  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  10  *
  11  * (C) Copyright 2006
  12  * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33 #include <common.h>
  34 #include <mpc5xxx.h>
  35 #include <pci.h>
  36
  37 #ifdef CONFIG_VIDEO_SM501
  38 #include <sm501.h>
  39 #endif
  40
  41 #if defined(CONFIG_MPC5200_DDR)
  42 #include "mt46v16m16-75.h"
  43 #else
  44 #include "mt48lc16m16a2-75.h"
  45 #endif
  46
  47 #ifdef CONFIG_RTC_MPC5200
  48 #include <rtc.h>
  49 #endif
  50
  51 #ifdef CONFIG_PS2MULT
  52 void ps2mult_early_init(void);
  53 #endif
  54
  55 #ifndef CFG_RAMBOOT
  56 static void sdram_start (int hi_addr)
  57 {
  58         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  59
  60         /* unlock mode register */
  61         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
  62                 hi_addr_bit;
  63         __asm__ volatile ("sync");
  64
  65         /* precharge all banks */
  66         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  67                 hi_addr_bit;
  68         __asm__ volatile ("sync");
  69
  70 #if SDRAM_DDR
  71         /* set mode register: extended mode */
  72         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  73         __asm__ volatile ("sync");
  74
  75         /* set mode register: reset DLL */
  76         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  77         __asm__ volatile ("sync");
  78 #endif
  79
  80         /* precharge all banks */
  81         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  82                 hi_addr_bit;
  83         __asm__ volatile ("sync");
  84
  85         /* auto refresh */
  86         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
  87                 hi_addr_bit;
  88         __asm__ volatile ("sync");
  89
  90         /* set mode register */
  91         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  92         __asm__ volatile ("sync");
  93
  94         /* normal operation */
  95         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  96         __asm__ volatile ("sync");
  97 }
  98 #endif
  99
 100 /*
 101  * ATTENTION: Although partially referenced initdram does NOT make real use
 102  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 103  *            is something else than 0x00000000.
 104  */
 105
 106 #if defined(CONFIG_MPC5200)
 107 long int initdram (int board_type)
 108 {
 109         ulong dramsize = 0;
 110         ulong dramsize2 = 0;
 111 #ifndef CFG_RAMBOOT
 112         ulong test1, test2;
 113
 114         /* setup SDRAM chip selects */
 115         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
 116         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
 117         __asm__ volatile ("sync");
 118
 119         /* setup config registers */
 120         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 121         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 122         __asm__ volatile ("sync");
 123
 124 #if SDRAM_DDR
 125         /* set tap delay */
 126         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 127         __asm__ volatile ("sync");
 128 #endif
 129
 130         /* find RAM size using SDRAM CS0 only */
 131         sdram_start(0);
 132         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
 133         sdram_start(1);
 134         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
 135         if (test1 > test2) {
 136                 sdram_start(0);
 137                 dramsize = test1;
 138         } else {
 139                 dramsize = test2;
 140         }
 141
 142         /* memory smaller than 1MB is impossible */
 143         if (dramsize < (1 << 20)) {
 144                 dramsize = 0;
 145         }
 146
 147         /* set SDRAM CS0 size according to the amount of RAM found */
 148         if (dramsize > 0) {
 149                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
 150                         __builtin_ffs(dramsize >> 20) - 1;
 151         } else {
 152                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 153         }
 154
 155         /* let SDRAM CS1 start right after CS0 */
 156         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
 157
 158         /* find RAM size using SDRAM CS1 only */
 159         sdram_start(0);
 160         test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
 161         sdram_start(1);
 162         test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
 163         if (test1 > test2) {
 164                 sdram_start(0);
 165                 dramsize2 = test1;
 166         } else {
 167                 dramsize2 = test2;
 168         }
 169
 170         /* memory smaller than 1MB is impossible */
 171         if (dramsize2 < (1 << 20)) {
 172                 dramsize2 = 0;
 173         }
 174
 175         /* set SDRAM CS1 size according to the amount of RAM found */
 176         if (dramsize2 > 0) {
 177                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 178                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 179         } else {
 180                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 181         }
 182
 183 #else /* CFG_RAMBOOT */
 184
 185         /* retrieve size of memory connected to SDRAM CS0 */
 186         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 187         if (dramsize >= 0x13) {
 188                 dramsize = (1 << (dramsize - 0x13)) << 20;
 189         } else {
 190                 dramsize = 0;
 191         }
 192
 193         /* retrieve size of memory connected to SDRAM CS1 */
 194         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 195         if (dramsize2 >= 0x13) {
 196                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 197         } else {
 198                 dramsize2 = 0;
 199         }
 200
 201 #endif /* CFG_RAMBOOT */
 202
 203         return dramsize;
 204 }
 205
 206 #elif defined(CONFIG_MGT5100)
 207
 208 long int initdram (int board_type)
 209 {
 210         ulong dramsize = 0;
 211 #ifndef CFG_RAMBOOT
 212         ulong test1, test2;
 213
 214         /* setup and enable SDRAM chip selects */
 215         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 216         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;    /* 2G           */
 217         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22);        /* Enable SDRAM */
 218         __asm__ volatile ("sync");
 219
 220         /* setup config registers */
 221         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 222         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 223
 224         /* address select register */
 225         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 226         __asm__ volatile ("sync");
 227
 228         /* find RAM size */
 229         sdram_start(0);
 230         test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 231         sdram_start(1);
 232         test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
 233         if (test1 > test2) {
 234                 sdram_start(0);
 235                 dramsize = test1;
 236         } else {
 237                 dramsize = test2;
 238         }
 239
 240         /* set SDRAM end address according to size */
 241         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 242
 243 #else /* CFG_RAMBOOT */
 244
 245         /* Retrieve amount of SDRAM available */
 246         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 247
 248 #endif /* CFG_RAMBOOT */
 249
 250         return dramsize;
 251 }
 252
 253 #else
 254 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 255 #endif
 256
 257 int checkboard (void)
 258 {
 259 #if defined (CONFIG_TQM5200)
 260         puts ("Board: TQM5200 (TQ-Components GmbH)\n");
 261 #endif
 262
 263 #if defined (CONFIG_BC3450)
 264         puts ("Dev:   GERSYS BC3450\n");
 265 #endif
 266
 267         return 0;
 268 }
 269
 270 void flash_preinit(void)
 271 {
 272         /*
 273          * Now, when we are in RAM, enable flash write
 274          * access for detection process.
 275          * Note that CS_BOOT cannot be cleared when
 276          * executing in flash.
 277          */
 278 #if defined(CONFIG_MGT5100)
 279         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);       /* disable CS_BOOT */
 280         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16);        /* enable CS0      */
 281 #endif
 282         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1;         /* clear RO        */
 283 }
 284
 285
 286 #ifdef  CONFIG_PCI
 287 static struct pci_controller hose;
 288
 289 extern void pci_mpc5xxx_init(struct pci_controller *);
 290
 291 void pci_init_board(void)
 292 {
 293         pci_mpc5xxx_init(&hose);
 294 }
 295 #endif
 296
 297 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 298 #define GPIO_PSC1_4     0x01000000UL
 299
 300 void init_ide_reset (void)
 301 {
 302         debug ("init_ide_reset\n");
 303
 304         /* Configure PSC1_4 as GPIO output for ATA reset */
 305         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 306         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 307 }
 308
 309 void ide_set_reset (int idereset)
 310 {
 311         debug ("ide_reset(%d)\n", idereset);
 312
 313         if (idereset) {
 314                 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
 315         } else {
 316                 *(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
 317         }
 318 }
 319 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
 320
 321 #ifdef CONFIG_POST
 322 /*
 323  * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
 324  * is left open, no keypress is detected.
 325  */
 326 int post_hotkeys_pressed(void)
 327 {
 328         struct mpc5xxx_gpio *gpio;
 329
 330         gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
 331
 332         /*
 333          * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
 334          * CODEC or UART mode. Consumer IrDA should still be possible.
 335          */
 336         gpio->port_config &= ~(0x07000000);
 337         gpio->port_config |=   0x03000000;
 338
 339         /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
 340         gpio->simple_gpioe |= 0x20000000;
 341
 342         /* Configure GPIO_IRDA_1 as input */
 343         gpio->simple_ddr &= ~(0x20000000);
 344
 345         return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
 346 }
 347 #endif
 348
 349 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 350
 351 void post_word_store (ulong a)
 352 {
 353         volatile ulong *save_addr =
 354                 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
 355
 356         *save_addr = a;
 357 }
 358
 359 ulong post_word_load (void)
 360 {
 361         volatile ulong *save_addr =
 362                 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
 363
 364         return *save_addr;
 365 }
 366 #endif  /* CONFIG_POST || CONFIG_LOGBUFFER*/
 367
 368
 369 #ifdef CONFIG_BOARD_EARLY_INIT_R
 370 int board_early_init_r (void)
 371 {
 372 #ifdef CONFIG_RTC_MPC5200
 373         struct rtc_time t;
 374
 375         /* set to Wed Dec 31 19:00:00 1969 */
 376         t.tm_sec = t.tm_min = 0;
 377         t.tm_hour = 19;
 378         t.tm_mday = 31;
 379         t.tm_mon = 12;
 380         t.tm_year = 1969;
 381         t.tm_wday = 3;
 382
 383         rtc_set(&t);
 384 #endif /* CONFIG_RTC_MPC5200 */
 385
 386 #ifdef CONFIG_PS2MULT
 387         ps2mult_early_init();
 388 #endif /* CONFIG_PS2MULT */
 389         return (0);
 390 }
 391 #endif /* CONFIG_BOARD_EARLY_INIT_R */
 392
 393
 394 int last_stage_init (void)
 395 {
 396         /*
 397          * auto scan for really existing devices and re-set chip select
 398          * configuration.
 399          */
 400         u16 save, tmp;
 401         int restore;
 402
 403         /*
 404          * Check for SRAM and SRAM size
 405          */
 406
 407         /* save original SRAM content  */
 408         save = *(volatile u16 *)CFG_CS2_START;
 409         restore = 1;
 410
 411         /* write test pattern to SRAM */
 412         *(volatile u16 *)CFG_CS2_START = 0xA5A5;
 413         __asm__ volatile ("sync");
 414         /*
 415          * Put a different pattern on the data lines: otherwise they may float
 416          * long enough to read back what we wrote.
 417          */
 418         tmp = *(volatile u16 *)CFG_FLASH_BASE;
 419         if (tmp == 0xA5A5)
 420                 puts ("!! possible error in SRAM detection\n");
 421
 422         if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
 423                 /* no SRAM at all, disable cs */
 424                 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
 425                 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
 426                 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
 427                 restore = 0;
 428                 __asm__ volatile ("sync");
 429         } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
 430                 /* make sure that we access a mirrored address */
 431                 *(volatile u16 *)CFG_CS2_START = 0x1111;
 432                 __asm__ volatile ("sync");
 433                 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
 434                         /* SRAM size = 512 kByte */
 435                         *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
 436                                                                 0x80000);
 437                         __asm__ volatile ("sync");
 438                         puts ("SRAM:  512 kB\n");
 439                 }
 440                 else
 441                         puts ("!! possible error in SRAM detection\n");
 442         } else {
 443                 puts ("SRAM:  1 MB\n");
 444         }
 445         /* restore origianl SRAM content  */
 446         if (restore) {
 447                 *(volatile u16 *)CFG_CS2_START = save;
 448                 __asm__ volatile ("sync");
 449         }
 450
 451         /*
 452          * Check for Grafic Controller
 453          */
 454
 455         /* save origianl FB content  */
 456         save = *(volatile u16 *)CFG_CS1_START;
 457         restore = 1;
 458
 459         /* write test pattern to FB memory */
 460         *(volatile u16 *)CFG_CS1_START = 0xA5A5;
 461         __asm__ volatile ("sync");
 462         /*
 463          * Put a different pattern on the data lines: otherwise they may float
 464          * long enough to read back what we wrote.
 465          */
 466         tmp = *(volatile u16 *)CFG_FLASH_BASE;
 467         if (tmp == 0xA5A5)
 468                 puts ("!! possible error in grafic controller detection\n");
 469
 470         if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
 471                 /* no grafic controller at all, disable cs */
 472                 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
 473                 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
 474                 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
 475                 restore = 0;
 476                 __asm__ volatile ("sync");
 477         } else {
 478                 puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
 479         }
 480         /* restore origianl FB content  */
 481         if (restore) {
 482                 *(volatile u16 *)CFG_CS1_START = save;
 483                 __asm__ volatile ("sync");
 484         }
 485
 486         return 0;
 487 }
 488
 489 #ifdef CONFIG_VIDEO_SM501
 490
 491 #define DISPLAY_WIDTH   640
 492 #define DISPLAY_HEIGHT  480
 493
 494 #ifdef CONFIG_VIDEO_SM501_8BPP
 495 #error CONFIG_VIDEO_SM501_8BPP not supported.
 496 #endif /* CONFIG_VIDEO_SM501_8BPP */
 497
 498 #ifdef CONFIG_VIDEO_SM501_16BPP
 499 #error CONFIG_VIDEO_SM501_16BPP not supported.
 500 #endif /* CONFIG_VIDEO_SM501_16BPP */
 501
 502 #ifdef CONFIG_VIDEO_SM501_32BPP
 503 static const SMI_REGS init_regs [] =
 504 {
 505 #if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
 506         /* FP only */
 507         {0x00004, 0x0},
 508         {0x00048, 0x00021807},
 509         {0x0004C, 0x091a0a01},
 510         {0x00054, 0x1},
 511         {0x00040, 0x00021807},
 512         {0x00044, 0x091a0a01},
 513         {0x00054, 0x0},
 514         {0x80000, 0x01013106},
 515         {0x80004, 0xc428bb17},
 516         {0x80000, 0x03013106},
 517         {0x8000C, 0x00000000},
 518         {0x80010, 0x0a000a00},
 519         {0x80014, 0x02800000},
 520         {0x80018, 0x01e00000},
 521         {0x8001C, 0x00000000},
 522         {0x80020, 0x01e00280},
 523         {0x80024, 0x02fa027f},
 524         {0x80028, 0x004a028b},
 525         {0x8002C, 0x020c01df},
 526         {0x80030, 0x000201e9},
 527         {0x80200, 0x00010200},
 528         {0x80000, 0x0f013106},
 529 #elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
 530         /* CRT only */
 531         {0x00004, 0x0},
 532         {0x00048, 0x00021807},
 533         {0x0004C, 0x10090a01},
 534         {0x00054, 0x1},
 535         {0x00040, 0x00021807},
 536         {0x00044, 0x10090a01},
 537         {0x00054, 0x0},
 538         {0x80200, 0x00010000},
 539         {0x80204, 0x0},
 540         {0x80208, 0x0A000A00},
 541         {0x8020C, 0x02fa027f},
 542         {0x80210, 0x004a028b},
 543         {0x80214, 0x020c01df},
 544         {0x80218, 0x000201e9},
 545         {0x80200, 0x00013306},
 546 #else   /* panel + CRT */
 547         {0x00004, 0x0},
 548         {0x00048, 0x00021807},
 549         {0x0004C, 0x091a0a01},
 550         {0x00054, 0x1},
 551         {0x00040, 0x00021807},
 552         {0x00044, 0x091a0a01},
 553         {0x00054, 0x0},
 554         {0x80000, 0x0f013106},
 555         {0x80004, 0xc428bb17},
 556         {0x8000C, 0x00000000},
 557         {0x80010, 0x0a000a00},
 558         {0x80014, 0x02800000},
 559         {0x80018, 0x01e00000},
 560         {0x8001C, 0x00000000},
 561         {0x80020, 0x01e00280},
 562         {0x80024, 0x02fa027f},
 563         {0x80028, 0x004a028b},
 564         {0x8002C, 0x020c01df},
 565         {0x80030, 0x000201e9},
 566         {0x80200, 0x00010000},
 567 #endif
 568         {0, 0}
 569 };
 570 #endif /* CONFIG_VIDEO_SM501_32BPP */
 571
 572 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 573 /*
 574  * Return text to be printed besides the logo.
 575  */
 576 void video_get_info_str (int line_number, char *info)
 577 {
 578         if (line_number == 1) {
 579 #if defined (CONFIG_TQM5200)
 580             strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
 581 #else
 582 #error No supported board selected
 583 #endif /* CONFIG_TQM5200 */
 584
 585 #if defined (CONFIG_BC3450)
 586         } else if (line_number == 2) {
 587             strcpy (info, " Dev:   GERSYS BC3450");
 588 #endif /* CONFIG_BC3450 */
 589         }
 590         else {
 591                 info [0] = '\0';
 592         }
 593 }
 594 #endif
 595
 596 /*
 597  * Returns SM501 register base address. First thing called in the
 598  * driver. Checks if SM501 is physically present.
 599  */
 600 unsigned int board_video_init (void)
 601 {
 602         u16 save, tmp;
 603         int restore, ret;
 604
 605         /*
 606          * Check for Grafic Controller
 607          */
 608
 609         /* save origianl FB content  */
 610         save = *(volatile u16 *)CFG_CS1_START;
 611         restore = 1;
 612
 613         /* write test pattern to FB memory */
 614         *(volatile u16 *)CFG_CS1_START = 0xA5A5;
 615         __asm__ volatile ("sync");
 616         /*
 617          * Put a different pattern on the data lines: otherwise they may float
 618          * long enough to read back what we wrote.
 619          */
 620         tmp = *(volatile u16 *)CFG_FLASH_BASE;
 621         if (tmp == 0xA5A5)
 622                 puts ("!! possible error in grafic controller detection\n");
 623
 624         if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
 625                 /* no grafic controller found */
 626                 restore = 0;
 627                 ret = 0;
 628         } else {
 629             ret = SM501_MMIO_BASE;
 630         }
 631
 632         if (restore) {
 633                 *(volatile u16 *)CFG_CS1_START = save;
 634                 __asm__ volatile ("sync");
 635         }
 636         return ret;
 637 }
 638
 639 /*
 640  * Returns SM501 framebuffer address
 641  */
 642 unsigned int board_video_get_fb (void)
 643 {
 644         return SM501_FB_BASE;
 645 }
 646
 647 /*
 648  * Called after initializing the SM501 and before clearing the screen.
 649  */
 650 void board_validate_screen (unsigned int base)
 651 {
 652 }
 653
 654 /*
 655  * Return a pointer to the initialization sequence.
 656  */
 657 const SMI_REGS *board_get_regs (void)
 658 {
 659         return init_regs;
 660 }
 661
 662 int board_get_width (void)
 663 {
 664         return DISPLAY_WIDTH;
 665 }
 666
 667 int board_get_height (void)
 668 {
 669         return DISPLAY_HEIGHT;
 670 }
 671
 672 #endif /* CONFIG_VIDEO_SM501 */