board/calao/sbc35_a9g20/sbc35_a9g20.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * Copyright (C) 2009
   7  * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/at91sam9260_matrix.h>
  15 #include <asm/arch/at91sam9_smc.h>
  16 #include <asm/arch/at91_common.h>
  17 #include <asm/arch/at91_pmc.h>
  18 #include <asm/arch/at91_rstc.h>
  19 #include <asm/arch/gpio.h>
  20
  21 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  22 #include <net.h>
  23 #endif
  24 #include <netdev.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 /* ------------------------------------------------------------------------- */
  29 /*
  30  * Miscelaneous platform dependent initialisations
  31  */
  32
  33 #ifdef CONFIG_CMD_NAND
  34 static void sbc35_a9g20_nand_hw_init(void)
  35 {
  36         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  37         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  38         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  39         unsigned long csa;
  40
  41         /* Enable CS3 */
  42         csa = readl(&matrix->ebicsa);
  43         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  44         writel(csa, &matrix->ebicsa);
  45
  46         /* Configure SMC CS3 for NAND/SmartMedia */
  47         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  48                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  49                 &smc->cs[3].setup);
  50         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  51                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  52                 &smc->cs[3].pulse);
  53         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  54                 &smc->cs[3].cycle);
  55         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  56                 AT91_SMC_MODE_EXNW_DISABLE |
  57 #ifdef CONFIG_SYS_NAND_DBW_16
  58                 AT91_SMC_MODE_DBW_16 |
  59 #else /* CONFIG_SYS_NAND_DBW_8 */
  60                 AT91_SMC_MODE_DBW_8 |
  61 #endif
  62                 AT91_SMC_MODE_TDF_CYCLE(2),
  63                 &smc->cs[3].mode);
  64
  65         writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  66
  67         /* Configure RDY/BSY */
  68         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  69
  70         /* Enable NandFlash */
  71         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  72 }
  73 #endif
  74
  75 #ifdef CONFIG_MACB
  76 static void sbc35_a9g20_macb_hw_init(void)
  77 {
  78         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  79         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  80         struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
  81         unsigned long erstl;
  82
  83         /* Enable EMAC clock */
  84         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  85
  86         /*
  87          * Disable pull-up on:
  88          *      RXDV (PA17) => PHY normal mode (not Test mode)
  89          *      ERX0 (PA14) => PHY ADDR0
  90          *      ERX1 (PA15) => PHY ADDR1
  91          *      ERX2 (PA25) => PHY ADDR2
  92          *      ERX3 (PA26) => PHY ADDR3
  93          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
  94          *
  95          * PHY has internal pull-down
  96          */
  97         writel(pin_to_mask(AT91_PIN_PA14) |
  98                pin_to_mask(AT91_PIN_PA15) |
  99                pin_to_mask(AT91_PIN_PA17) |
 100                pin_to_mask(AT91_PIN_PA25) |
 101                pin_to_mask(AT91_PIN_PA26) |
 102                pin_to_mask(AT91_PIN_PA28),
 103                &pioa->pudr);
 104
 105         erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 106
 107         /* Need to reset PHY -> 500ms reset */
 108         writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
 109                 AT91_RSTC_MR_URSTEN, &rstc->mr);
 110
 111         writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 112
 113         /* Wait for end hardware reset */
 114         while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
 115                 ;
 116
 117         /* Restore NRST value */
 118         writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
 119                 &rstc->mr);
 120
 121         /* Re-enable pull-up */
 122         writel(pin_to_mask(AT91_PIN_PA14) |
 123                pin_to_mask(AT91_PIN_PA15) |
 124                pin_to_mask(AT91_PIN_PA17) |
 125                pin_to_mask(AT91_PIN_PA25) |
 126                pin_to_mask(AT91_PIN_PA26) |
 127                pin_to_mask(AT91_PIN_PA28),
 128                &pioa->puer);
 129
 130         at91_macb_hw_init();
 131 }
 132 #endif
 133
 134 int board_init(void)
 135 {
 136         /* adress of boot parameters */
 137         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 138
 139         at91_seriald_hw_init();
 140         sbc35_a9g20_nand_hw_init();
 141 #ifdef CONFIG_ATMEL_SPI
 142         at91_spi0_hw_init(1 << 4 | 1 << 5);
 143 #endif
 144 #ifdef CONFIG_MACB
 145         sbc35_a9g20_macb_hw_init();
 146 #endif
 147
 148         return 0;
 149 }
 150
 151 int dram_init(void)
 152 {
 153         gd->ram_size = get_ram_size(
 154                 (void *)CONFIG_SYS_SDRAM_BASE,
 155                 CONFIG_SYS_SDRAM_SIZE);
 156         return 0;
 157 }
 158
 159 #ifdef CONFIG_RESET_PHY_R
 160 void reset_phy(void)
 161 {
 162 }
 163 #endif
 164
 165 int board_eth_init(bd_t *bis)
 166 {
 167         int rc = 0;
 168 #ifdef CONFIG_MACB
 169         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 170 #endif
 171         return rc;
 172 }