2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Based on mx6qsabrelite.c file
4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5 * Leo Sartre, <lsartre@adeneo-embedded.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/sata.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/mxc_i2c.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
24 #include <fsl_esdhc.h>
26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h>
29 #include <ipu_pixfmt.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
34 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
41 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
42 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
44 #define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
48 gd
->ram_size
= get_ram_size((void *)PHYS_SDRAM
, PHYS_SDRAM_SIZE
);
53 static iomux_v3_cfg_t
const uart2_pads
[] = {
54 MX6_PAD_EIM_D26__UART2_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
55 MX6_PAD_EIM_D27__UART2_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
58 static iomux_v3_cfg_t
const usdhc2_pads
[] = {
59 MX6_PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
60 MX6_PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
61 MX6_PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
62 MX6_PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
63 MX6_PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
64 MX6_PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
65 MX6_PAD_GPIO_4__GPIO1_IO04
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
68 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
69 MX6_PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
70 MX6_PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
71 MX6_PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
72 MX6_PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
73 MX6_PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
74 MX6_PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
75 MX6_PAD_SD3_DAT4__SD3_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
76 MX6_PAD_SD3_DAT5__SD3_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
77 MX6_PAD_SD3_DAT6__SD3_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
78 MX6_PAD_SD3_DAT7__SD3_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
79 MX6_PAD_SD3_RST__SD3_RESET
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
82 static iomux_v3_cfg_t
const usdhc4_pads
[] = {
83 MX6_PAD_SD4_CLK__SD4_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
84 MX6_PAD_SD4_CMD__SD4_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
85 MX6_PAD_SD4_DAT0__SD4_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
86 MX6_PAD_SD4_DAT1__SD4_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
87 MX6_PAD_SD4_DAT2__SD4_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
88 MX6_PAD_SD4_DAT3__SD4_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
89 MX6_PAD_SD4_DAT4__SD4_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
90 MX6_PAD_SD4_DAT5__SD4_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
91 MX6_PAD_SD4_DAT6__SD4_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
92 MX6_PAD_SD4_DAT7__SD4_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
93 MX6_PAD_NANDF_D6__GPIO2_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
), /* CD */
96 static iomux_v3_cfg_t
const usb_otg_pads
[] = {
97 MX6_PAD_EIM_D22__USB_OTG_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
),
98 MX6_PAD_GPIO_1__USB_OTG_ID
| MUX_PAD_CTRL(NO_PAD_CTRL
),
101 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
102 struct i2c_pads_info i2c_pad_info1
= {
104 .i2c_mode
= MX6_PAD_KEY_COL3__I2C2_SCL
| PC
,
105 .gpio_mode
= MX6_PAD_KEY_COL3__GPIO4_IO12
| PC
,
106 .gp
= IMX_GPIO_NR(4, 12)
109 .i2c_mode
= MX6_PAD_KEY_ROW3__I2C2_SDA
| PC
,
110 .gpio_mode
= MX6_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
111 .gp
= IMX_GPIO_NR(4, 13)
115 #define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */
117 struct interface_level
{
122 static struct interface_level mipi_levels
[] = {
127 /* setup board specific PMIC */
128 int power_init_board(void)
135 /* configure I2C multiplexer */
136 gpio_direction_output(MX6Q_QMX6_PFUZE_MUX
, 1);
138 power_pfuze100_init(I2C_PMIC
);
139 p
= pmic_get("PFUZE100");
147 pmic_reg_read(p
, PFUZE100_DEVICEID
, &id1
);
148 pmic_reg_read(p
, PFUZE100_REVID
, &id2
);
149 printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1
, id2
);
154 /* set level of MIPI if specified */
155 lv_mipi
= getenv("lv_mipi");
159 for (i
= 0; i
< ARRAY_SIZE(mipi_levels
); i
++) {
160 if (!strcmp(mipi_levels
[i
].name
, lv_mipi
)) {
161 printf("set MIPI level %s\n",
162 mipi_levels
[i
].name
);
163 ret
= pmic_reg_write(p
, PFUZE100_VGEN4VOL
,
164 mipi_levels
[i
].value
);
173 static void setup_iomux_uart(void)
175 imx_iomux_v3_setup_multiple_pads(uart2_pads
, ARRAY_SIZE(uart2_pads
));
178 #ifdef CONFIG_FSL_ESDHC
179 static struct fsl_esdhc_cfg usdhc_cfg
[] = {
185 int board_mmc_getcd(struct mmc
*mmc
)
187 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
190 switch (cfg
->esdhc_base
) {
191 case USDHC2_BASE_ADDR
:
192 gpio_direction_input(IMX_GPIO_NR(1, 4));
193 ret
= !gpio_get_value(IMX_GPIO_NR(1, 4));
195 case USDHC3_BASE_ADDR
:
196 ret
= 1; /* eMMC is always present */
198 case USDHC4_BASE_ADDR
:
199 gpio_direction_input(IMX_GPIO_NR(2, 6));
200 ret
= !gpio_get_value(IMX_GPIO_NR(2, 6));
203 printf("Bad USDHC interface\n");
209 int board_mmc_init(bd_t
*bis
)
214 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
215 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
216 usdhc_cfg
[2].sdhc_clk
= mxc_get_clock(MXC_ESDHC4_CLK
);
218 imx_iomux_v3_setup_multiple_pads(usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
219 imx_iomux_v3_setup_multiple_pads(usdhc3_pads
, ARRAY_SIZE(usdhc3_pads
));
220 imx_iomux_v3_setup_multiple_pads(usdhc4_pads
, ARRAY_SIZE(usdhc4_pads
));
222 for (i
= 0; i
< ARRAY_SIZE(usdhc_cfg
); i
++) {
223 status
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
232 int board_ehci_hcd_init(int port
)
236 imx_iomux_v3_setup_multiple_pads(usb_otg_pads
,
237 ARRAY_SIZE(usb_otg_pads
));
239 * set daisy chain for otg_pin_id on 6q.
240 * for 6dl, this bit is reserved
242 imx_iomux_set_gpr_register(1, 13, 1, 1);
248 printf("Invalid USB port: %d\n", port
);
255 int board_ehci_power(int port
, int on
)
261 gpio_direction_output(IMX_GPIO_NR(5, 5), on
);
264 printf("Invalid USB port: %d\n", port
);
271 struct display_info_t
{
275 int (*detect
)(struct display_info_t
const *dev
);
276 void (*enable
)(struct display_info_t
const *dev
);
277 struct fb_videomode mode
;
280 static void disable_lvds(struct display_info_t
const *dev
)
282 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
284 clrbits_le32(&iomux
->gpr
[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK
|
285 IOMUXC_GPR2_LVDS_CH1_MODE_MASK
);
288 static void do_enable_hdmi(struct display_info_t
const *dev
)
291 imx_enable_hdmi_phy();
294 static struct display_info_t
const displays
[] = {
298 .pixfmt
= IPU_PIX_FMT_RGB666
,
315 .vmode
= FB_VMODE_NONINTERLACED
} },
319 .pixfmt
= IPU_PIX_FMT_RGB24
,
321 .enable
= do_enable_hdmi
,
335 .vmode
= FB_VMODE_NONINTERLACED
} }
338 int board_video_skip(void)
342 char const *panel
= getenv("panel");
344 for (i
= 0; i
< ARRAY_SIZE(displays
); i
++) {
345 struct display_info_t
const *dev
= displays
+ i
;
346 if (dev
->detect
&& dev
->detect(dev
)) {
347 panel
= dev
->mode
.name
;
348 printf("auto-detected panel %s\n", panel
);
353 panel
= displays
[0].mode
.name
;
354 printf("No panel detected: default to %s\n", panel
);
358 for (i
= 0; i
< ARRAY_SIZE(displays
); i
++) {
359 if (!strcmp(panel
, displays
[i
].mode
.name
))
363 if (i
< ARRAY_SIZE(displays
)) {
364 ret
= ipuv3_fb_init(&displays
[i
].mode
, 0, displays
[i
].pixfmt
);
366 if (displays
[i
].enable
)
367 displays
[i
].enable(displays
+ i
);
368 printf("Display: %s (%ux%u)\n",
369 displays
[i
].mode
.name
, displays
[i
].mode
.xres
,
370 displays
[i
].mode
.yres
);
372 printf("LCD %s cannot be configured: %d\n",
373 displays
[i
].mode
.name
, ret
);
375 printf("unsupported panel %s\n", panel
);
382 static void setup_display(void)
384 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
385 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
391 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
392 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_LDB_DI0_MASK
|
393 MXC_CCM_CCGR3_LDB_DI1_MASK
);
395 /* set LDB0, LDB1 clk select to 011/011 */
396 reg
= readl(&mxc_ccm
->cs2cdr
);
397 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
398 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
);
399 reg
|= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
) |
400 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
);
401 writel(reg
, &mxc_ccm
->cs2cdr
);
403 setbits_le32(&mxc_ccm
->cscmr2
, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV
|
404 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV
);
406 setbits_le32(&mxc_ccm
->chsccdr
, CHSCCDR_CLK_SEL_LDB_DI0
<<
407 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
|
408 CHSCCDR_CLK_SEL_LDB_DI0
<<
409 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET
);
411 reg
= IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
412 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
413 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
414 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
415 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
416 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
417 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
418 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
419 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
;
420 writel(reg
, &iomux
->gpr
[2]);
422 reg
= readl(&iomux
->gpr
[3]);
423 reg
= (reg
& ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
|
424 IOMUXC_GPR3_HDMI_MUX_CTL_MASK
)) |
425 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<
426 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET
);
427 writel(reg
, &iomux
->gpr
[3]);
431 * Do not overwrite the console
432 * Use always serial for U-Boot console
434 int overwrite_console(void)
439 int board_early_init_f(void)
449 /* address of boot parameters */
450 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
452 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info1
);
454 #ifdef CONFIG_CMD_SATA
463 puts("Board: Conga-QEVAL QMX6 Quad\n");
468 #ifdef CONFIG_CMD_BMODE
469 static const struct boot_mode board_boot_modes
[] = {
470 /* 4 bit bus width */
471 {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
472 {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
477 int misc_init_r(void)
479 #ifdef CONFIG_CMD_BMODE
480 add_board_boot_modes(board_boot_modes
);