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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / cpc45 / cpc45.c
1 /*
2 * (C) Copyright 2001
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <mpc824x.h>
26 #include <asm/processor.h>
27 #include <asm/io.h>
28 #include <pci.h>
29 #include <i2c.h>
30 #include <netdev.h>
31
32 int sysControlDisplay(int digit, uchar ascii_code);
33 extern void Plx9030Init(void);
34 extern void SPD67290Init(void);
35
36 /* We have to clear the initial data area here. Couldn't have done it
37 * earlier because DRAM had not been initialized.
38 */
39 int board_early_init_f(void)
40 {
41
42 /* enable DUAL UART Mode on CPC45 */
43 *(uchar*)DUART_DCR |= 0x1; /* set DCM bit */
44
45 return 0;
46 }
47
48 int checkboard(void)
49 {
50 /*
51 char revision = BOARD_REV;
52 */
53 ulong busfreq = get_bus_freq(0);
54 char buf[32];
55
56 puts ("CPC45 ");
57 /*
58 printf("Revision %d ", revision);
59 */
60 printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
61
62 return 0;
63 }
64
65 phys_size_t initdram (int board_type)
66 {
67 int m, row, col, bank, i, ref;
68 unsigned long start, end;
69 uint32_t mccr1, mccr2;
70 uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
71 uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
72 uint8_t mber = 0;
73 unsigned int tmp;
74
75 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
76
77 if (i2c_reg_read (0x50, 2) != 0x04)
78 return 0; /* Memory type */
79
80 m = i2c_reg_read (0x50, 5); /* # of physical banks */
81 row = i2c_reg_read (0x50, 3); /* # of rows */
82 col = i2c_reg_read (0x50, 4); /* # of columns */
83 bank = i2c_reg_read (0x50, 17); /* # of logical banks */
84 ref = i2c_reg_read (0x50, 12); /* refresh rate / type */
85
86 CONFIG_READ_WORD(MCCR1, mccr1);
87 mccr1 &= 0xffff0000;
88
89 CONFIG_READ_WORD(MCCR2, mccr2);
90 mccr2 &= 0xffff0000;
91
92 start = CONFIG_SYS_SDRAM_BASE;
93 end = start + (1 << (col + row + 3) ) * bank - 1;
94
95 for (i = 0; i < m; i++) {
96 mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
97 if (i < 4) {
98 msar1 |= ((start >> 20) & 0xff) << i * 8;
99 emsar1 |= ((start >> 28) & 0xff) << i * 8;
100 mear1 |= ((end >> 20) & 0xff) << i * 8;
101 emear1 |= ((end >> 28) & 0xff) << i * 8;
102 } else {
103 msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
104 emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
105 mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
106 emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
107 }
108 mber |= 1 << i;
109 start += (1 << (col + row + 3) ) * bank;
110 end += (1 << (col + row + 3) ) * bank;
111 }
112 for (; i < 8; i++) {
113 if (i < 4) {
114 msar1 |= 0xff << i * 8;
115 emsar1 |= 0x30 << i * 8;
116 mear1 |= 0xff << i * 8;
117 emear1 |= 0x30 << i * 8;
118 } else {
119 msar2 |= 0xff << (i-4) * 8;
120 emsar2 |= 0x30 << (i-4) * 8;
121 mear2 |= 0xff << (i-4) * 8;
122 emear2 |= 0x30 << (i-4) * 8;
123 }
124 }
125
126 switch(ref) {
127 case 0x00:
128 case 0x80:
129 tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
130 break;
131 case 0x01:
132 case 0x81:
133 tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
134 break;
135 case 0x02:
136 case 0x82:
137 tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
138 break;
139 case 0x03:
140 case 0x83:
141 tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
142 break;
143 case 0x04:
144 case 0x84:
145 tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
146 break;
147 case 0x05:
148 case 0x85:
149 tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
150 break;
151 default:
152 tmp = 0x512;
153 break;
154 }
155
156 CONFIG_WRITE_WORD(MCCR1, mccr1);
157 CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
158 CONFIG_WRITE_WORD(MSAR1, msar1);
159 CONFIG_WRITE_WORD(EMSAR1, emsar1);
160 CONFIG_WRITE_WORD(MEAR1, mear1);
161 CONFIG_WRITE_WORD(EMEAR1, emear1);
162 CONFIG_WRITE_WORD(MSAR2, msar2);
163 CONFIG_WRITE_WORD(EMSAR2, emsar2);
164 CONFIG_WRITE_WORD(MEAR2, mear2);
165 CONFIG_WRITE_WORD(EMEAR2, emear2);
166 CONFIG_WRITE_BYTE(MBER, mber);
167
168 return (1 << (col + row + 3) ) * bank * m;
169 }
170
171
172 /*
173 * Initialize PCI Devices, report devices found.
174 */
175
176 static struct pci_config_table pci_cpc45_config_table[] = {
177 #ifndef CONFIG_PCI_PNP
178 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
179 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
180 PCI_ENET0_MEMADDR,
181 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
182 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
183 pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
184 PCI_PLX9030_MEMADDR,
185 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
186 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
187 pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
188 PCMCIA_IO_BASE,
189 PCI_COMMAND_MEMORY | PCI_COMMAND_IO }},
190 #endif /*CONFIG_PCI_PNP*/
191 { }
192 };
193
194 struct pci_controller hose = {
195 #ifndef CONFIG_PCI_PNP
196 config_table: pci_cpc45_config_table,
197 #endif
198 };
199
200 void pci_init_board(void)
201 {
202 pci_mpc824x_init(&hose);
203
204 /* init PCI_to_LOCAL Bus BRIDGE */
205 Plx9030Init();
206
207 /* Clear Display */
208 DISP_CWORD = 0x0;
209
210 sysControlDisplay(0,' ');
211 sysControlDisplay(1,'C');
212 sysControlDisplay(2,'P');
213 sysControlDisplay(3,'C');
214 sysControlDisplay(4,' ');
215 sysControlDisplay(5,'4');
216 sysControlDisplay(6,'5');
217 sysControlDisplay(7,' ');
218
219 }
220
221 /**************************************************************************
222 *
223 * sysControlDisplay - controls one of the Alphanum. Display digits.
224 *
225 * This routine will write an ASCII character to the display digit requested.
226 *
227 * SEE ALSO:
228 *
229 * RETURNS: NA
230 */
231
232 int sysControlDisplay (int digit, /* number of digit 0..7 */
233 uchar ascii_code /* ASCII code */
234 )
235 {
236 if ((digit < 0) || (digit > 7))
237 return (-1);
238
239 *((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
240
241 return (0);
242 }
243
244 #if defined(CONFIG_CMD_PCMCIA)
245
246 #ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
247 volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
248 #endif
249
250 int pcmcia_init(void)
251 {
252 u_int rc;
253
254 debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
255
256 rc = i82365_init();
257
258 return rc;
259 }
260
261 #endif
262
263 # ifdef CONFIG_IDE_LED
264 void ide_led (uchar led, uchar status)
265 {
266 u_char val;
267 /* We have one PCMCIA slot and use LED H4 for the IDE Interface */
268 val = readb(BCSR_BASE + 0x04);
269 if (status) { /* led on */
270 val |= B_CTRL_LED0;
271 } else {
272 val &= ~B_CTRL_LED0;
273 }
274 writeb(val, BCSR_BASE + 0x04);
275 }
276 # endif
277
278 int board_eth_init(bd_t *bis)
279 {
280 return pci_eth_init(bis);
281 }