1 /******************************************************************************
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
21 *****************************************************************************/
25 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
27 #include <ppc_asm.tmpl>
30 #include <asm/cache.h>
33 #define LI32(reg,val) \
37 #define WDCR_EBC(reg,val) \
44 #define WDCR_SDRAM(reg,val) \
51 /******************************************************************************
52 * Function: ext_bus_cntlr_init
54 * Description: Configures EBC Controller and a few basic chip selects.
56 * CS0 is setup to get the Boot Flash out of the addresss range
57 * so that we may setup a stack. CS7 is setup so that we can
58 * access and reset the hardware watchdog.
60 * IMPORTANT: For pass1 this code must run from
61 * cache since you can not reliably change a peripheral banks
62 * timing register (pbxap) while running code from that bank.
63 * For ex., since we are running from ROM on bank 0, we can NOT
64 * execute the code that modifies bank 0 timings from ROM, so
65 * we run it from cache.
67 * Notes: Does NOT use the stack.
68 *****************************************************************************/
71 .globl ext_bus_cntlr_init
72 .type ext_bus_cntlr_init, @function
75 /********************************************************************
76 * Prefetch entire ext_bus_cntrl_init function into the icache.
77 * This is necessary because we are going to change the same CS we
78 * are executing from. Otherwise a CPU lockup may occur.
79 *******************************************************************/
82 mflr r3 /* get address of ..getAddr */
84 /* Calculate number of cache lines for this function */
85 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
88 icbt r0, r3 /* prefetch cache line for addr in r3*/
89 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
90 bdnz ..ebcloop /* continue for $CTR cache lines */
92 /********************************************************************
93 * Delay to ensure all accesses to ROM are complete before changing
94 * bank 0 timings. 200usec should be enough.
95 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
96 *******************************************************************/
98 ori r3, r3, 0xA000 /* wait 200us from reset */
101 bdnz ..spinlp /* spin loop */
103 /********************************************************************
105 *******************************************************************/
109 /********************************************************************
110 * Setup CPC0_CR1: Change PCIINT signal to PerWE
111 *******************************************************************/
116 /********************************************************************
117 * Setup External Bus Controller (EBC).
118 *******************************************************************/
119 WDCR_EBC(epcr, 0xd84c0000)
120 /********************************************************************
121 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
122 *******************************************************************/
123 /*WDCR_EBC(pb0ap, 0x03055200)*/
124 /*WDCR_EBC(pb0ap, 0x04055200)*/
125 WDCR_EBC(pb0ap, 0x08055200)
126 WDCR_EBC(pb0cr, 0xff87a000)
127 /********************************************************************
128 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
129 *******************************************************************/
130 /*WDCR_EBC(pb3ap, 0x07869200)*/
131 WDCR_EBC(pb3ap, 0x04055200)
132 WDCR_EBC(pb3cr, 0xf081c000)
133 /********************************************************************
134 * Memory Bank 1,2,4-7 (Unused) initialization
135 *******************************************************************/
149 /* We are all done */
150 mtlr r0 /* Restore link register */
151 blr /* Return to calling function */
152 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
153 /* end ext_bus_cntlr_init() */
155 /******************************************************************************
156 * Function: sdram_init
158 * Description: Configures SDRAM memory banks.
160 * Notes: Does NOT use the stack.
161 *****************************************************************************/
165 .type sdram_init, @function
169 * Disable memory controller to allow
170 * values to be changed.
172 WDCR_SDRAM(mem_mcopt1, 0x00000000)
175 * Configure Memory Banks
177 WDCR_SDRAM(mem_mb0cf, 0x00062001)
178 WDCR_SDRAM(mem_mb1cf, 0x00000000)
179 WDCR_SDRAM(mem_mb2cf, 0x00000000)
180 WDCR_SDRAM(mem_mb3cf, 0x00000000)
183 * Set up SDTR1 (SDRAM Timing Register)
185 WDCR_SDRAM(mem_sdtr1, 0x00854009)
188 * Set RTR (Refresh Timing Register)
190 WDCR_SDRAM(mem_rtr, 0x10000000)
191 /* WDCR_SDRAM(mem_rtr, 0x05f00000) */
193 /********************************************************************
194 * Delay to ensure 200usec have elapsed since reset. Assume worst
195 * case that the core is running 200Mhz:
196 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
197 *******************************************************************/
199 ori r3, r3, 0xA000 /* Wait >200us from reset */
202 bdnz ..spinlp2 /* spin loop */
204 /********************************************************************
205 * Set memory controller options reg, MCOPT1.
206 *******************************************************************/
207 WDCR_SDRAM(mem_mcopt1,0x80800000)
210 blr /* Return to calling function */
211 .Lfe1: .size sdram_init,.Lfe1-sdram_init
212 /* end sdram_init() */