board/davedenx/aria/aria.c

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2009 Dave Srl www.dave.eu
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/bitops.h>
  10 #include <command.h>
  11 #include <asm/io.h>
  12 #include <asm/processor.h>
  13 #include <asm/mpc512x.h>
  14 #include <fdt_support.h>
  15 #ifdef CONFIG_MISC_INIT_R
  16 #include <i2c.h>
  17 #endif
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 int dram_init(void)
  22 {
  23         gd->ram_size = fixed_sdram(NULL, NULL, 0);
  24
  25         return 0;
  26 }
  27
  28 int misc_init_r(void)
  29 {
  30         u32 tmp;
  31
  32         tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
  33         printf("FPGA:  %u-%u.%u.%u\n",
  34                 (tmp & 0xFF000000) >> 24,
  35                 (tmp & 0x00FF0000) >> 16,
  36                 (tmp & 0x0000FF00) >>  8,
  37                  tmp & 0x000000FF
  38         );
  39
  40         return 0;
  41 }
  42
  43 static  iopin_t ioregs_init[] = {
  44         /*
  45          * FEC
  46          */
  47
  48         /* FEC on PSCx_x*/
  49         {
  50                 offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
  51                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  52                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  53         },
  54         {
  55                 offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
  56                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  57                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  58         },
  59         {
  60                 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
  61                 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  62                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  63         },
  64
  65         /*
  66          * DIU
  67          */
  68         /* FUNC2=DIU CLK */
  69         {
  70                 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
  71                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  72                 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
  73         },
  74         /* FUNC2=DIU_HSYNC */
  75         {
  76                 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
  77                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  78                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  79         },
  80         /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
  81         {
  82                 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
  83                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  84                 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  85         },
  86         /*
  87          * On board SRAM
  88          */
  89         /* FUNC2=/LPC CS6 */
  90         {
  91                 offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
  92                 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  93                 IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
  94         },
  95 };
  96
  97 int checkboard (void)
  98 {
  99         puts("Board: ARIA\n");
 100
 101         /* initialize function mux & slew rate IO inter alia on IO Pins  */
 102
 103         iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
 104
 105         return 0;
 106 }
 107
 108 #ifdef CONFIG_OF_BOARD_SETUP
 109 int ft_board_setup(void *blob, bd_t *bd)
 110 {
 111         ft_cpu_setup(blob, bd);
 112
 113         return 0;
 114 }
 115 #endif /* CONFIG_OF_BOARD_SETUP */