board/davedenx/qong/qong.c

   1 /*
   2  *
   3  * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <netdev.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/io.h>
  29 #include <nand.h>
  30 #include <fsl_pmic.h>
  31 #include <mxc_gpio.h>
  32 #include "qong_fpga.h"
  33 #include <watchdog.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_HW_WATCHDOG
  38 void hw_watchdog_reset(void)
  39 {
  40         mxc_hw_watchdog_reset();
  41 }
  42 #endif
  43
  44 int dram_init (void)
  45 {
  46         /* dram_init must store complete ramsize in gd->ram_size */
  47         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  48                                 PHYS_SDRAM_1_SIZE);
  49         return 0;
  50 }
  51
  52 static void qong_fpga_reset(void)
  53 {
  54         mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
  55         udelay(30);
  56         mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
  57
  58         udelay(300);
  59 }
  60
  61 int board_early_init_f (void)
  62 {
  63 #ifdef CONFIG_QONG_FPGA
  64         /* CS1: FPGA/Network Controller/GPIO */
  65         /* 16-bit, no DTACK */
  66         __REG(CSCR_U(1)) = 0x00000A01;
  67         __REG(CSCR_L(1)) = 0x20040501;
  68         __REG(CSCR_A(1)) = 0x04020C00;
  69
  70         /* setup pins for FPGA */
  71         mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
  72         mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
  73         mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
  74         mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
  75         mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
  76
  77         /* FPGA reset  Pin */
  78         /* rstn = 0 */
  79         mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
  80         mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
  81
  82         /* set interrupt pin as input */
  83         mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
  84
  85         /* FPGA JTAG Interface */
  86         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
  87         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
  88         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
  89         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
  90         mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
  91         mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
  92         mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
  93         mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
  94 #endif
  95
  96         /* setup pins for UART1 */
  97         mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  98         mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
  99         mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
 100         mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 101
 102         /* setup pins for SPI (pmic) */
 103         mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
 104         mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
 105         mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
 106         mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
 107         mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
 108
 109         /* Setup pins for USB2 Host */
 110         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
 111         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
 112         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
 113         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
 114         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
 115         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
 116         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
 117         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
 118         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
 119         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
 120         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
 121         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
 122
 123 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 124                         PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 125
 126         mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
 127         mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
 128         mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
 129         mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
 130         mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
 131         mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
 132         mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);       /* USBH2_DATA2 */
 133         mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);       /* USBH2_DATA3 */
 134         mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);        /* USBH2_DATA4 */
 135         mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);        /* USBH2_DATA5 */
 136         mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);       /* USBH2_DATA6 */
 137         mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);       /* USBH2_DATA7 */
 138
 139         writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
 140
 141         return 0;
 142
 143 }
 144
 145 int board_init (void)
 146 {
 147         /* Chip selects */
 148         /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
 149         /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
 150         __REG(CSCR_U(0)) = ((0 << 31)   | /* SP */
 151                                                 (0 << 30)       | /* WP */
 152                                                 (0 << 28)       | /* BCD */
 153                                                 (0 << 24)       | /* BCS */
 154                                                 (0 << 22)       | /* PSZ */
 155                                                 (0 << 21)       | /* PME */
 156                                                 (0 << 20)       | /* SYNC */
 157                                                 (0 << 16)       | /* DOL */
 158                                                 (3 << 14)       | /* CNC */
 159                                                 (21 << 8)       | /* WSC */
 160                                                 (0 << 7)        | /* EW */
 161                                                 (0 << 4)        | /* WWS */
 162                                                 (6 << 0)          /* EDC */
 163                                            );
 164
 165         __REG(CSCR_L(0)) = ((2 << 28)   | /* OEA */
 166                                                 (1 << 24)       | /* OEN */
 167                                                 (3 << 20)       | /* EBWA */
 168                                                 (3 << 16)       | /* EBWN */
 169                                                 (1 << 12)       | /* CSA */
 170                                                 (1 << 11)       | /* EBC */
 171                                                 (5 << 8)        | /* DSZ */
 172                                                 (1 << 4)        | /* CSN */
 173                                                 (0 << 3)        | /* PSR */
 174                                                 (0 << 2)        | /* CRE */
 175                                                 (0 << 1)        | /* WRAP */
 176                                                 (1 << 0)          /* CSEN */
 177                                            );
 178
 179         __REG(CSCR_A(0)) = ((2 << 28)   | /* EBRA */
 180                                                 (1 << 24)       | /* EBRN */
 181                                                 (2 << 20)       | /* RWA */
 182                                                 (2 << 16)       | /* RWN */
 183                                                 (0 << 15)       | /* MUM */
 184                                                 (0 << 13)       | /* LAH */
 185                                                 (2 << 10)       | /* LBN */
 186                                                 (0 << 8)        | /* LBA */
 187                                                 (0 << 6)        | /* DWW */
 188                                                 (0 << 4)        | /* DCT */
 189                                                 (0 << 3)        | /* WWU */
 190                                                 (0 << 2)        | /* AGE */
 191                                                 (0 << 1)        | /* CNC2 */
 192                                                 (0 << 0)          /* FCE */
 193                                            );
 194
 195         /* board id for linux */
 196         gd->bd->bi_arch_number = MACH_TYPE_QONG;
 197         gd->bd->bi_boot_params = (0x80000100);  /* adress of boot parameters */
 198
 199         qong_fpga_init();
 200
 201         return 0;
 202 }
 203
 204 int board_late_init(void)
 205 {
 206         u32 val;
 207
 208         /* Enable RTC battery */
 209         val = pmic_reg_read(REG_POWER_CTL0);
 210         pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
 211         pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
 212
 213 #ifdef CONFIG_HW_WATCHDOG
 214         mxc_hw_watchdog_enable();
 215 #endif
 216
 217         return 0;
 218 }
 219
 220 int checkboard (void)
 221 {
 222         printf("Board: DAVE/DENX Qong\n");
 223         return 0;
 224 }
 225
 226 int misc_init_r (void)
 227 {
 228 #ifdef CONFIG_QONG_FPGA
 229         u32 tmp;
 230
 231         tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
 232         printf("FPGA:  ");
 233         printf("version register = %u.%u.%u\n",
 234                 (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
 235 #endif
 236         return 0;
 237 }
 238
 239 int board_eth_init(bd_t *bis)
 240 {
 241 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
 242         return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
 243 #else
 244         return 0;
 245 #endif
 246 }
 247
 248 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
 249 static void board_nand_setup(void)
 250 {
 251
 252         /* CS3: NAND 8-bit */
 253         __REG(CSCR_U(3)) = 0x00004f00;
 254         __REG(CSCR_L(3)) = 0x20013b31;
 255         __REG(CSCR_A(3)) = 0x00020800;
 256         __REG(IOMUXC_GPR) |= 1 << 13;
 257
 258         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
 259         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
 260         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
 261
 262         /* Make sure to reset the fpga else you cannot access NAND */
 263         qong_fpga_reset();
 264
 265         /* Enable NAND flash */
 266         mxc_gpio_set(15, 1);
 267         mxc_gpio_set(14, 1);
 268         mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT);
 269         mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN);
 270         mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN);
 271         mxc_gpio_set(15, 0);
 272
 273 }
 274
 275 int qong_nand_rdy(void *chip)
 276 {
 277         udelay(1);
 278         return mxc_gpio_get(16);
 279 }
 280
 281 void qong_nand_select_chip(struct mtd_info *mtd, int chip)
 282 {
 283         if (chip >= 0)
 284                 mxc_gpio_set(15, 0);
 285         else
 286                 mxc_gpio_set(15, 1);
 287
 288 }
 289
 290 void qong_nand_plat_init(void *chip)
 291 {
 292         struct nand_chip *nand = (struct nand_chip *)chip;
 293         nand->chip_delay = 20;
 294         nand->select_chip = qong_nand_select_chip;
 295         nand->options &= ~NAND_BUSWIDTH_16;
 296         board_nand_setup();
 297 }
 298
 299 #endif