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1 /*
2 * Copyright (C) 2009 Texas Instruments Incorporated
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <nand.h>
9 #include <asm/io.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/emif_defs.h>
12 #include <asm/arch/nand_defs.h>
13 #include <asm/arch/gpio.h>
14 #include <netdev.h>
15 #include <asm/arch/davinci_misc.h>
16 #ifdef CONFIG_DAVINCI_MMC
17 #include <mmc.h>
18 #include <asm/arch/sdmmc_defs.h>
19 #endif
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 int board_init(void)
24 {
25 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
26 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
27
28 return 0;
29 }
30
31 #ifdef CONFIG_DRIVER_TI_EMAC
32 int board_eth_init(bd_t *bis)
33 {
34 uint8_t eeprom_enetaddr[6];
35 int i;
36 struct davinci_gpio *gpio1_base =
37 (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
38
39 /* Configure PINMUX 3 to enable EMAC pins */
40 writel((readl(PINMUX3) | 0x1affff), PINMUX3);
41
42 /* Configure GPIO20 as output */
43 writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir);
44
45 /* Toggle GPIO 20 */
46 for (i = 0; i < 20; i++) {
47 /* GPIO 20 low */
48 writel((readl(&gpio1_base->out_data) & ~(1 << 20)),
49 &gpio1_base->out_data);
50
51 udelay(1000);
52
53 /* GPIO 20 high */
54 writel((readl(&gpio1_base->out_data) | (1 << 20)),
55 &gpio1_base->out_data);
56 }
57
58 /* Configure I2C pins so that EEPROM can be read */
59 writel((readl(PINMUX3) | 0x01400000), PINMUX3);
60
61 /* Read Ethernet MAC address from EEPROM */
62 if (dvevm_read_mac_address(eeprom_enetaddr))
63 davinci_sync_env_enetaddr(eeprom_enetaddr);
64
65 davinci_emac_initialize();
66
67 return 0;
68 }
69 #endif
70
71 #ifdef CONFIG_NAND_DAVINCI
72 static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
73 {
74 struct nand_chip *this = mtd->priv;
75 unsigned long wbase = (unsigned long) this->IO_ADDR_W;
76 unsigned long rbase = (unsigned long) this->IO_ADDR_R;
77
78 if (chip == 1) {
79 __set_bit(14, &wbase);
80 __set_bit(14, &rbase);
81 } else {
82 __clear_bit(14, &wbase);
83 __clear_bit(14, &rbase);
84 }
85 this->IO_ADDR_W = (void *)wbase;
86 this->IO_ADDR_R = (void *)rbase;
87 }
88
89 int board_nand_init(struct nand_chip *nand)
90 {
91 davinci_nand_init(nand);
92 nand->select_chip = nand_dm365evm_select_chip;
93 return 0;
94 }
95 #endif
96
97 #ifdef CONFIG_DAVINCI_MMC
98 static struct davinci_mmc mmc_sd0 = {
99 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
100 .input_clk = 121500000,
101 .host_caps = MMC_MODE_4BIT,
102 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
103 .version = MMC_CTLR_VERSION_2,
104 };
105
106 #ifdef CONFIG_DAVINCI_MMC_SD1
107 static struct davinci_mmc mmc_sd1 = {
108 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
109 .input_clk = 121500000,
110 .host_caps = MMC_MODE_4BIT,
111 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
112 .version = MMC_CTLR_VERSION_2,
113 };
114 #endif
115
116 int board_mmc_init(bd_t *bis)
117 {
118 int err;
119
120 /* Add slot-0 to mmc subsystem */
121 err = davinci_mmc_init(bis, &mmc_sd0);
122 if (err)
123 return err;
124
125 #ifdef CONFIG_DAVINCI_MMC_SD1
126 #define PUPDCTL1 0x01c4007c
127 /* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */
128 writel((readl(PINMUX4) | 0x55400000), PINMUX4);
129 writel((readl(PINMUX0) | 0x00010000), PINMUX0);
130
131 /* Configure MMC/SD pins as pullup */
132 writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
133
134 /* Add slot-1 to mmc subsystem */
135 err = davinci_mmc_init(bis, &mmc_sd1);
136 #endif
137
138 return err;
139 }
140 #endif