2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/pxa-regs.h>
27 DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
41 /* Set up GPIO pins first */
44 /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
53 /* tebrandt - ASCR, clear the RDH bit */
56 bic r1, r1, #0x80000000
60 /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
67 /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
69 ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
70 /* ldr r1, =0x80000403 */
72 ldr r1, [r0] /* delay until written */
74 /* 3. wait nop power up waiting period (200ms)
75 * optimization: Steps 4+6 can be done during this
79 /* 4. Perform an initial Rcomp-calibration cycle */
83 ldr r1, [r0] /* delay until written */
84 /* missing: program for automatic rcomp evaluation cycles */
86 /* 5. DDR DRAM strobe delay calibration */
91 ldr r1, [r0] /* delay until written */
99 /* Configure MDREFR */
105 /* Enable the dynamic memory controller */
108 orr r1, r1, #MDCNFG_DMCEN
111 #ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
112 /* scrub/init SDRAM if enabled/present */
113 ldr r8, =CONFIG_SYS_DRAM_BASE /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
114 ldr r9, =CONFIG_SYS_DRAM_SIZE /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
115 mov r0, #0 /* scrub with 0x0000:0000 */
123 10: /* fastScrubLoop */
124 subs r9, r9, #32 /* 8 words/line */
128 #endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
131 /* Mask all interrupts */
133 mcr p6, 0, r1, c1, c0, 0 @ ICMR
135 /* Disable software and data breakpoints */
137 mcr p15,0,r0,c14,c8,0 /* ibcr0 */
138 mcr p15,0,r0,c14,c9,0 /* ibcr1 */
139 mcr p15,0,r0,c14,c4,0 /* dbcon */
141 /* Enable all debug functionality */
143 mcr p14,0,r0,c10,c0,0 /* dcsr */