board/egnite/ethernut5/ethernut5.c

   1 /*
   2  * (C) Copyright 2011
   3  * egnite GmbH <info@egnite.de>
   4  *
   5  * (C) Copyright 2010
   6  * Ole Reinhardt <ole.reinhardt@thermotemp.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * Ethernut 5 general board support
  13  *
  14  * Ethernut is an open source hardware and software project for
  15  * embedded Ethernet devices. Hardware layouts and CAD files are
  16  * freely available under BSD-like license.
  17  *
  18  * Ethernut 5 is the first member of the Ethernut board family
  19  * with U-Boot and Linux support. This implementation is based
  20  * on the original work done by Ole Reinhardt, but heavily modified
  21  * to support additional features and the latest board revision 5.0F.
  22  *
  23  * Main board components are by default:
  24  *
  25  * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
  26  * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
  27  * 512 MBytes Micron MT29F4G08ABADA NAND Flash
  28  * 4 MBytes Atmel AT45DB321D DataFlash
  29  * SMSC LAN8710 Ethernet PHY
  30  * Atmel ATmega168 MCU used for power management
  31  * Linear Technology LTC4411 PoE controller
  32  *
  33  * U-Boot relevant board interfaces are:
  34  *
  35  * 100 Mbit Ethernet with IEEE 802.3af PoE
  36  * RS-232 serial port
  37  * USB host and device
  38  * MMC/SD-Card slot
  39  * Expansion port with I2C, SPI and more...
  40  *
  41  * Typically the U-Boot image is loaded from serial DataFlash into
  42  * SDRAM by the samboot boot loader, which is located in internal
  43  * NOR Flash and provides all essential initializations like CPU
  44  * and peripheral clocks and, of course, the SDRAM configuration.
  45  *
  46  * For testing purposes it is also possibly to directly transfer
  47  * the image into SDRAM via JTAG. A tested configuration exists
  48  * for the Turtelizer 2 hardware dongle and the OpenOCD software.
  49  * In this case the latter will do the basic hardware configuration
  50  * via its reset-init script.
  51  *
  52  * For additional information visit the project home page at
  53  * http://www.ethernut.de/
  54  */
  55
  56 #include <common.h>
  57 #include <net.h>
  58 #include <netdev.h>
  59 #include <miiphy.h>
  60 #include <i2c.h>
  61 #include <spi.h>
  62 #include <dataflash.h>
  63 #include <mmc.h>
  64 #include <atmel_mci.h>
  65
  66 #include <asm/arch/at91sam9260.h>
  67 #include <asm/arch/at91sam9260_matrix.h>
  68 #include <asm/arch/at91sam9_smc.h>
  69 #include <asm/arch/at91_common.h>
  70 #include <asm/arch/at91_pmc.h>
  71 #include <asm/arch/at91_spi.h>
  72 #include <asm/arch/gpio.h>
  73 #include <asm/io.h>
  74
  75 #include "ethernut5_pwrman.h"
  76
  77 DECLARE_GLOBAL_DATA_PTR;
  78
  79 AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
  80
  81 struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
  82         {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
  83 };
  84
  85 /*
  86  * In fact we have 7 partitions, but u-boot supports 5 only. This is
  87  * no big deal, because the first partition is reserved for applications
  88  * and the last one is used by Nut/OS. Both need not to be visible here.
  89  */
  90 dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
  91         { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
  92         { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
  93         { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
  94         { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
  95         { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
  96 };
  97
  98 /*
  99  * This is called last during early initialization. Most of the basic
 100  * hardware interfaces are up and running.
 101  *
 102  * The SDRAM hardware has been configured by the first stage boot loader.
 103  * We only need to announce its size, using u-boot's memory check.
 104  */
 105 int dram_init(void)
 106 {
 107         gd->ram_size = get_ram_size(
 108                         (void *)CONFIG_SYS_SDRAM_BASE,
 109                         CONFIG_SYS_SDRAM_SIZE);
 110         return 0;
 111 }
 112
 113 #ifdef CONFIG_CMD_NAND
 114 static void ethernut5_nand_hw_init(void)
 115 {
 116         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 117         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 118         unsigned long csa;
 119
 120         /* Assign CS3 to NAND/SmartMedia Interface */
 121         csa = readl(&matrix->ebicsa);
 122         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
 123         writel(csa, &matrix->ebicsa);
 124
 125         /* Configure SMC CS3 for NAND/SmartMedia */
 126         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
 127                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
 128                 &smc->cs[3].setup);
 129         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
 130                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
 131                 &smc->cs[3].pulse);
 132         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
 133                 &smc->cs[3].cycle);
 134         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 135                 AT91_SMC_MODE_EXNW_DISABLE |
 136                 AT91_SMC_MODE_DBW_8 |
 137                 AT91_SMC_MODE_TDF_CYCLE(2),
 138                 &smc->cs[3].mode);
 139
 140 #ifdef CONFIG_SYS_NAND_READY_PIN
 141         /* Ready pin is optional. */
 142         at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 143 #endif
 144         at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 145 }
 146 #endif
 147
 148 /*
 149  * This is called first during late initialization.
 150  */
 151 int board_init(void)
 152 {
 153         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 154
 155         /* Enable clocks for all PIOs */
 156         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 157                 (1 << ATMEL_ID_PIOC),
 158                 &pmc->pcer);
 159         /* Set adress of boot parameters. */
 160         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 161         /* Initialize UARTs and power management. */
 162         at91_seriald_hw_init();
 163         ethernut5_power_init();
 164 #ifdef CONFIG_CMD_NAND
 165         ethernut5_nand_hw_init();
 166 #endif
 167 #ifdef CONFIG_HAS_DATAFLASH
 168         at91_spi0_hw_init(1 << 0);
 169 #endif
 170         return 0;
 171 }
 172
 173 #ifdef CONFIG_MACB
 174 /*
 175  * This is optionally called last during late initialization.
 176  */
 177 int board_eth_init(bd_t *bis)
 178 {
 179         const char *devname;
 180         unsigned short mode;
 181         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 182
 183         /* Enable on-chip EMAC clock. */
 184         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 185         /* Need to reset PHY via power management. */
 186         ethernut5_phy_reset();
 187         /* Set peripheral pins. */
 188         at91_macb_hw_init();
 189         /* Basic EMAC initialization. */
 190         if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
 191                 return -1;
 192         /*
 193          * Early board revisions have a pull-down at the PHY's MODE0
 194          * strap pin, which forces the PHY into power down. Here we
 195          * switch to all-capable mode.
 196          */
 197         devname = miiphy_get_current_dev();
 198         if (miiphy_read(devname, 0, 18, &mode) == 0) {
 199                 /* Set mode[2:0] to 0b111. */
 200                 mode |= 0x00E0;
 201                 miiphy_write(devname, 0, 18, mode);
 202                 /* Soft reset overrides strap pins. */
 203                 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
 204         }
 205         /* Sync environment with network devices, needed for nfsroot. */
 206         return eth_init(gd->bd);
 207 }
 208 #endif
 209
 210 #ifdef CONFIG_GENERIC_ATMEL_MCI
 211 int board_mmc_init(bd_t *bd)
 212 {
 213         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 214
 215         /* Enable MCI clock. */
 216         writel(1 << ATMEL_ID_MCI, &pmc->pcer);
 217         /* Initialize MCI hardware. */
 218         at91_mci_hw_init();
 219         /* Register the device. */
 220         return atmel_mci_init((void *)ATMEL_BASE_MCI);
 221 }
 222
 223 int board_mmc_getcd(struct mmc *mmc)
 224 {
 225         return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
 226 }
 227 #endif
 228
 229 #ifdef CONFIG_ATMEL_SPI
 230 /*
 231  * Note, that u-boot uses different code for SPI bus access. While
 232  * memory routines use automatic chip select control, the serial
 233  * flash support requires 'manual' GPIO control. Thus, we switch
 234  * modes.
 235  */
 236 void spi_cs_activate(struct spi_slave *slave)
 237 {
 238         /* Enable NPCS0 in GPIO mode. This disables peripheral control. */
 239         at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
 240 }
 241
 242 void spi_cs_deactivate(struct spi_slave *slave)
 243 {
 244         /* Disable NPCS0 in GPIO mode. */
 245         at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
 246         /* Switch back to peripheral chip select control. */
 247         at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
 248 }
 249
 250 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 251 {
 252         return bus == 0 && cs == 0;
 253 }
 254 #endif