2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/sizes.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/iomux-v3.h>
23 DECLARE_GLOBAL_DATA_PTR
;
27 /* Address of boot parameters */
28 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
33 #ifdef CONFIG_ENV_IS_IN_MMC
34 int board_mmc_get_env_dev(int devno
)
36 /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
37 return (devno
== 3) ? 1 : 0;
40 static void mmc_late_init(void)
44 u32 dev_no
= mmc_get_env_dev();
46 setenv_ulong("mmcdev", dev_no
);
49 sprintf(mmcblk
, "/dev/mmcblk%dp2 rootwait rw", dev_no
);
50 setenv("mmcroot", mmcblk
);
52 sprintf(cmd
, "mmc dev %d", dev_no
);
57 int board_late_init(void)
59 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK
) >>
65 #ifdef CONFIG_ENV_IS_IN_MMC
68 setenv("modeboot", "mmcboot");
71 setenv("modeboot", "");
76 setenv("fdt_file", "imx6q-icore-rqs.dtb");
77 else if(is_mx6dl() || is_mx6solo())
78 setenv("fdt_file", "imx6dl-icore-rqs.dtb");
85 gd
->ram_size
= imx_ddr_size();
90 #ifdef CONFIG_SPL_BUILD
94 #include <asm/arch/crm_regs.h>
95 #include <asm/arch/mx6-ddr.h>
97 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
98 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
99 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
101 static iomux_v3_cfg_t
const uart4_pads
[] = {
102 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
103 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
106 /* MMC board initialization is needed till adding DM support in SPL */
107 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
109 #include <fsl_esdhc.h>
111 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
112 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
113 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
115 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
116 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
117 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
118 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
119 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
120 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
121 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
124 static iomux_v3_cfg_t
const usdhc4_pads
[] = {
125 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
126 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
127 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
128 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
129 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
130 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
131 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
132 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
133 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
134 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
137 struct fsl_esdhc_cfg usdhc_cfg
[2] = {
138 {USDHC3_BASE_ADDR
, 1, 4},
139 {USDHC4_BASE_ADDR
, 1, 8},
142 int board_mmc_getcd(struct mmc
*mmc
)
144 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
147 switch (cfg
->esdhc_base
) {
148 case USDHC3_BASE_ADDR
:
149 case USDHC4_BASE_ADDR
:
157 int board_mmc_init(bd_t
*bis
)
162 * According to the board_mmc_init() the following map is done:
163 * (U-boot device node) (Physical Port)
167 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
170 SETUP_IOMUX_PADS(usdhc3_pads
);
171 usdhc_cfg
[i
].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
174 SETUP_IOMUX_PADS(usdhc4_pads
);
175 usdhc_cfg
[i
].sdhc_clk
= mxc_get_clock(MXC_ESDHC4_CLK
);
178 printf("Warning - USDHC%d controller not supporting\n",
183 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
185 printf("Warning: failed to initialize mmc dev %d\n", i
);
193 #ifdef CONFIG_ENV_IS_IN_MMC
194 void board_boot_order(u32
*spl_boot_list
)
196 u32 bmode
= imx6_src_get_boot_mode();
197 u8 boot_dev
= BOOT_DEVICE_MMC1
;
199 switch ((bmode
& IMX6_BMODE_MASK
) >> IMX6_BMODE_SHIFT
) {
202 /* SD/eSD - BOOT_DEVICE_MMC1 */
205 case IMX6_BMODE_EMMC
:
207 boot_dev
= BOOT_DEVICE_MMC2
;
210 /* Default - BOOT_DEVICE_MMC1 */
211 printf("Wrong board boot order\n");
215 spl_boot_list
[0] = boot_dev
;
220 #ifdef CONFIG_SPL_LOAD_FIT
221 int board_fit_config_name_match(const char *name
)
223 if (is_mx6dq() && !strcmp(name
, "imx6q-icore-rqs"))
225 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name
, "imx6dl-icore-rqs"))
238 #define IMX6DQ_DRIVE_STRENGTH 0x30
239 #define IMX6SDL_DRIVE_STRENGTH 0x28
241 /* configure MX6Q/DUAL mmdc DDR io registers */
242 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
243 .dram_sdqs0
= IMX6DQ_DRIVE_STRENGTH
,
244 .dram_sdqs1
= IMX6DQ_DRIVE_STRENGTH
,
245 .dram_sdqs2
= IMX6DQ_DRIVE_STRENGTH
,
246 .dram_sdqs3
= IMX6DQ_DRIVE_STRENGTH
,
247 .dram_sdqs4
= IMX6DQ_DRIVE_STRENGTH
,
248 .dram_sdqs5
= IMX6DQ_DRIVE_STRENGTH
,
249 .dram_sdqs6
= IMX6DQ_DRIVE_STRENGTH
,
250 .dram_sdqs7
= IMX6DQ_DRIVE_STRENGTH
,
251 .dram_dqm0
= IMX6DQ_DRIVE_STRENGTH
,
252 .dram_dqm1
= IMX6DQ_DRIVE_STRENGTH
,
253 .dram_dqm2
= IMX6DQ_DRIVE_STRENGTH
,
254 .dram_dqm3
= IMX6DQ_DRIVE_STRENGTH
,
255 .dram_dqm4
= IMX6DQ_DRIVE_STRENGTH
,
256 .dram_dqm5
= IMX6DQ_DRIVE_STRENGTH
,
257 .dram_dqm6
= IMX6DQ_DRIVE_STRENGTH
,
258 .dram_dqm7
= IMX6DQ_DRIVE_STRENGTH
,
259 .dram_cas
= IMX6DQ_DRIVE_STRENGTH
,
260 .dram_ras
= IMX6DQ_DRIVE_STRENGTH
,
261 .dram_sdclk_0
= IMX6DQ_DRIVE_STRENGTH
,
262 .dram_sdclk_1
= IMX6DQ_DRIVE_STRENGTH
,
263 .dram_reset
= IMX6DQ_DRIVE_STRENGTH
,
264 .dram_sdcke0
= IMX6DQ_DRIVE_STRENGTH
,
265 .dram_sdcke1
= IMX6DQ_DRIVE_STRENGTH
,
266 .dram_sdba2
= 0x00000000,
267 .dram_sdodt0
= IMX6DQ_DRIVE_STRENGTH
,
268 .dram_sdodt1
= IMX6DQ_DRIVE_STRENGTH
,
271 /* configure MX6Q/DUAL mmdc GRP io registers */
272 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
273 .grp_b0ds
= IMX6DQ_DRIVE_STRENGTH
,
274 .grp_b1ds
= IMX6DQ_DRIVE_STRENGTH
,
275 .grp_b2ds
= IMX6DQ_DRIVE_STRENGTH
,
276 .grp_b3ds
= IMX6DQ_DRIVE_STRENGTH
,
277 .grp_b4ds
= IMX6DQ_DRIVE_STRENGTH
,
278 .grp_b5ds
= IMX6DQ_DRIVE_STRENGTH
,
279 .grp_b6ds
= IMX6DQ_DRIVE_STRENGTH
,
280 .grp_b7ds
= IMX6DQ_DRIVE_STRENGTH
,
281 .grp_addds
= IMX6DQ_DRIVE_STRENGTH
,
282 .grp_ddrmode_ctl
= 0x00020000,
283 .grp_ddrpke
= 0x00000000,
284 .grp_ddrmode
= 0x00020000,
285 .grp_ctlds
= IMX6DQ_DRIVE_STRENGTH
,
286 .grp_ddr_type
= 0x000c0000,
289 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
290 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
291 .dram_sdclk_0
= IMX6SDL_DRIVE_STRENGTH
,
292 .dram_sdclk_1
= IMX6SDL_DRIVE_STRENGTH
,
293 .dram_cas
= IMX6SDL_DRIVE_STRENGTH
,
294 .dram_ras
= IMX6SDL_DRIVE_STRENGTH
,
295 .dram_reset
= IMX6SDL_DRIVE_STRENGTH
,
296 .dram_sdcke0
= IMX6SDL_DRIVE_STRENGTH
,
297 .dram_sdcke1
= IMX6SDL_DRIVE_STRENGTH
,
298 .dram_sdba2
= 0x00000000,
299 .dram_sdodt0
= IMX6SDL_DRIVE_STRENGTH
,
300 .dram_sdodt1
= IMX6SDL_DRIVE_STRENGTH
,
301 .dram_sdqs0
= IMX6SDL_DRIVE_STRENGTH
,
302 .dram_sdqs1
= IMX6SDL_DRIVE_STRENGTH
,
303 .dram_sdqs2
= IMX6SDL_DRIVE_STRENGTH
,
304 .dram_sdqs3
= IMX6SDL_DRIVE_STRENGTH
,
305 .dram_sdqs4
= IMX6SDL_DRIVE_STRENGTH
,
306 .dram_sdqs5
= IMX6SDL_DRIVE_STRENGTH
,
307 .dram_sdqs6
= IMX6SDL_DRIVE_STRENGTH
,
308 .dram_sdqs7
= IMX6SDL_DRIVE_STRENGTH
,
309 .dram_dqm0
= IMX6SDL_DRIVE_STRENGTH
,
310 .dram_dqm1
= IMX6SDL_DRIVE_STRENGTH
,
311 .dram_dqm2
= IMX6SDL_DRIVE_STRENGTH
,
312 .dram_dqm3
= IMX6SDL_DRIVE_STRENGTH
,
313 .dram_dqm4
= IMX6SDL_DRIVE_STRENGTH
,
314 .dram_dqm5
= IMX6SDL_DRIVE_STRENGTH
,
315 .dram_dqm6
= IMX6SDL_DRIVE_STRENGTH
,
316 .dram_dqm7
= IMX6SDL_DRIVE_STRENGTH
,
319 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
320 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
321 .grp_ddr_type
= 0x000c0000,
322 .grp_ddrmode_ctl
= 0x00020000,
323 .grp_ddrpke
= 0x00000000,
324 .grp_addds
= IMX6SDL_DRIVE_STRENGTH
,
325 .grp_ctlds
= IMX6SDL_DRIVE_STRENGTH
,
326 .grp_ddrmode
= 0x00020000,
327 .grp_b0ds
= IMX6SDL_DRIVE_STRENGTH
,
328 .grp_b1ds
= IMX6SDL_DRIVE_STRENGTH
,
329 .grp_b2ds
= IMX6SDL_DRIVE_STRENGTH
,
330 .grp_b3ds
= IMX6SDL_DRIVE_STRENGTH
,
331 .grp_b4ds
= IMX6SDL_DRIVE_STRENGTH
,
332 .grp_b5ds
= IMX6SDL_DRIVE_STRENGTH
,
333 .grp_b6ds
= IMX6SDL_DRIVE_STRENGTH
,
334 .grp_b7ds
= IMX6SDL_DRIVE_STRENGTH
,
338 static struct mx6_ddr3_cfg mt41j256
= {
352 static struct mx6_mmdc_calibration mx6dq_mmdc_calib
= {
353 .p0_mpwldectrl0
= 0x000E0009,
354 .p0_mpwldectrl1
= 0x0018000E,
355 .p1_mpwldectrl0
= 0x00000007,
356 .p1_mpwldectrl1
= 0x00000000,
357 .p0_mpdgctrl0
= 0x43280334,
358 .p0_mpdgctrl1
= 0x031C0314,
359 .p1_mpdgctrl0
= 0x4318031C,
360 .p1_mpdgctrl1
= 0x030C0258,
361 .p0_mprddlctl
= 0x3E343A40,
362 .p1_mprddlctl
= 0x383C3844,
363 .p0_mpwrdlctl
= 0x40404440,
364 .p1_mpwrdlctl
= 0x4C3E4446,
368 static struct mx6_ddr_sysinfo mem_q
= {
369 .ddr_type
= DDR_TYPE_DDR3
,
372 /* config for full 4GB range so that get_mem_size() works */
385 static struct mx6_mmdc_calibration mx6dl_mmdc_calib
= {
386 .p0_mpwldectrl0
= 0x001F0024,
387 .p0_mpwldectrl1
= 0x00110018,
388 .p1_mpwldectrl0
= 0x001F0024,
389 .p1_mpwldectrl1
= 0x00110018,
390 .p0_mpdgctrl0
= 0x4230022C,
391 .p0_mpdgctrl1
= 0x02180220,
392 .p1_mpdgctrl0
= 0x42440248,
393 .p1_mpdgctrl1
= 0x02300238,
394 .p0_mprddlctl
= 0x44444A48,
395 .p1_mprddlctl
= 0x46484A42,
396 .p0_mpwrdlctl
= 0x38383234,
397 .p1_mpwrdlctl
= 0x3C34362E,
401 static struct mx6_ddr_sysinfo mem_dl
= {
404 /* config for full 4GB range so that get_mem_size() works */
417 /* DDR 32bit 512MB */
418 static struct mx6_ddr_sysinfo mem_s
= {
421 /* config for full 4GB range so that get_mem_size() works */
434 static void ccgr_init(void)
436 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
438 writel(0x00003F3F, &ccm
->CCGR0
);
439 writel(0x0030FC00, &ccm
->CCGR1
);
440 writel(0x000FC000, &ccm
->CCGR2
);
441 writel(0x3F300000, &ccm
->CCGR3
);
442 writel(0xFF00F300, &ccm
->CCGR4
);
443 writel(0x0F0000C3, &ccm
->CCGR5
);
444 writel(0x000003CC, &ccm
->CCGR6
);
447 static void gpr_init(void)
449 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
451 /* enable AXI cache for VDOA/VPU/IPU */
452 writel(0xF00000CF, &iomux
->gpr
[4]);
453 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
454 writel(0x007F007F, &iomux
->gpr
[6]);
455 writel(0x007F007F, &iomux
->gpr
[7]);
458 static void spl_dram_init(void)
461 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
462 mx6_dram_cfg(&mem_s
, &mx6dl_mmdc_calib
, &mt41j256
);
463 } else if (is_mx6dl()) {
464 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
465 mx6_dram_cfg(&mem_dl
, &mx6dl_mmdc_calib
, &mt41j256
);
466 } else if (is_mx6dq()) {
467 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
468 mx6_dram_cfg(&mem_q
, &mx6dq_mmdc_calib
, &mt41j256
);
474 void board_init_f(ulong dummy
)
478 /* setup AIPS and disable watchdog */
484 SETUP_IOMUX_PADS(uart4_pads
);
489 /* UART clocks enabled and gd valid - init serial console */
490 preloader_console_init();
492 /* DDR initialization */
496 memset(__bss_start
, 0, __bss_end
- __bss_start
);
498 /* load/boot image from boot device */
499 board_init_r(NULL
, 0);