2 * Copyright (C) 2005 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * Support for Embedded Planet EP88x boards.
6 * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * SDRAM uses two Micron chips.
32 * Minimal CPU frequency is 40MHz.
34 static uint sdram_table
[] = {
35 /* Single read (offset 0x00 in UPM RAM) */
36 0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
37 0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
39 /* Burst read (offset 0x08 in UPM RAM) */
40 0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
41 0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
42 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
43 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
45 /* Single write (offset 0x18 in UPM RAM) */
46 0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
47 0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
49 /* Burst write (offset 0x20 in UPM RAM) */
50 0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
51 0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
52 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
53 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
55 /* Refresh (offset 0x30 in UPM RAM) */
56 0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
57 0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
58 0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
60 /* Exception (offset 0x3C in UPM RAM) */
61 0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
64 int board_early_init_f (void)
66 vu_char
*bcsr
= (vu_char
*)CONFIG_SYS_BCSR
;
68 bcsr
[0] |= 0x0C; /* Turn the LEDs off */
69 bcsr
[2] |= 0x08; /* Enable flash WE# line - necessary for
70 flash detection by CFI driver
73 #if defined(CONFIG_8xx_CONS_SMC1)
74 bcsr
[6] |= 0x10; /* Enables RS-232 transceiver */
76 #if defined(CONFIG_8xx_CONS_SCC2)
77 bcsr
[7] |= 0x10; /* Enables RS-232 transceiver */
79 #ifdef CONFIG_ETHER_ON_FEC1
80 bcsr
[8] |= 0xC0; /* Enable Ethernet 1 PHY */
82 #ifdef CONFIG_ETHER_ON_FEC2
83 bcsr
[8] |= 0x30; /* Enable Ethernet 2 PHY */
89 phys_size_t
initdram (int board_type
)
92 volatile immap_t
*immap
= (volatile immap_t
*)CONFIG_SYS_IMMR
;
93 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
95 upmconfig(UPMA
, sdram_table
, sizeof(sdram_table
) / sizeof(uint
));
97 /* Configure SDRAM refresh */
98 memctl
->memc_mptpr
= MPTPR_PTP_DIV2
; /* BRGCLK/2 */
100 memctl
->memc_mamr
= (65 << 24) | CONFIG_SYS_MAMR
; /* No refresh */
103 /* Run MRS pattern from location 0x36 */
104 memctl
->memc_mar
= 0x88;
105 memctl
->memc_mcr
= 0x80002236;
108 memctl
->memc_mamr
|= MAMR_PTAE
; /* Enable refresh */
109 memctl
->memc_or1
= ~(CONFIG_SYS_SDRAM_MAX_SIZE
- 1) | OR_CSNT_SAM
;
110 memctl
->memc_br1
= CONFIG_SYS_SDRAM_BASE
| BR_PS_32
| BR_MS_UPMA
| BR_V
;
112 msize
= get_ram_size(CONFIG_SYS_SDRAM_BASE
, CONFIG_SYS_SDRAM_MAX_SIZE
);
113 memctl
->memc_or1
|= ~(msize
- 1);
118 int checkboard( void )
120 vu_char
*bcsr
= (vu_char
*)CONFIG_SYS_BCSR
;
128 printf("unknown ID=%02X", bcsr
[15]);
130 printf(" CPLD revision %d\n", bcsr
[14]);