2 * (C) Copyright 2005-2008
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * (C) Copyright 2001-2003
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
33 #include <asm/4xx_pci.h>
36 DECLARE_GLOBAL_DATA_PTR
;
40 extern int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]);
41 extern void lxt971_no_sleep(void);
42 extern ulong
flash_get_size (ulong base
, int banknum
);
44 int flash_banks
= CONFIG_SYS_MAX_FLASH_BANKS_DETECT
;
46 /* fpga configuration data - gzip compressed and generated by bin2c */
47 const unsigned char fpgadata
[] =
53 * include common fpga code (for esd boards)
55 #include "../common/fpga.c"
58 int gunzip(void *, int, unsigned char *, unsigned long *);
60 #ifdef CONFIG_LCD_USED
61 /* logo bitmap data - gzip compressed and generated by bin2c */
62 unsigned char logo_bmp
[] =
64 #include "logo_640_480_24bpp.c"
68 * include common lcd code (for esd boards)
70 #include "../common/lcd.c"
71 #include "../common/s1d13505_640_480_16bpp.h"
72 #include "../common/s1d13806_640_480_16bpp.h"
73 #endif /* CONFIG_LCD_USED */
76 * include common auto-update code (for esd boards)
78 #include "../common/auto_update.h"
80 au_image_t au_image
[] = {
81 {"preinst.img", 0, -1, AU_SCRIPT
},
82 {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE
| AU_PROTECT
},
83 {"pImage", 0xfe000000, 0x00100000, AU_NOR
| AU_PROTECT
},
84 {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR
| AU_PROTECT
},
85 {"work.img", 0xfe500000, 0x01400000, AU_NOR
},
86 {"data.img", 0xff900000, 0x00580000, AU_NOR
},
87 {"logo.img", 0xffe80000, 0x00100000, AU_NOR
| AU_PROTECT
},
88 {"postinst.img", 0, 0, AU_SCRIPT
},
91 int N_AU_IMAGES
= (sizeof(au_image
) / sizeof(au_image
[0]));
93 int board_revision(void)
95 unsigned long cntrl0Reg
;
96 volatile unsigned long value
;
99 * Get version of APC405 board from GPIO's
102 /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
103 cntrl0Reg
= mfdcr(cntrl0
);
104 mtdcr(cntrl0
, cntrl0Reg
| 0x03800000);
105 out_be32((void*)GPIO0_ODR
, in_be32((void*)GPIO0_ODR
) & ~0x001c0000);
106 out_be32((void*)GPIO0_TCR
, in_be32((void*)GPIO0_TCR
) & ~0x001c0000);
108 /* wait some time before reading input */
111 /* get config bits */
112 value
= in_be32((void*)GPIO0_IR
) & 0x001c0000;
114 * Restore GPIO settings
116 mtdcr(cntrl0
, cntrl0Reg
);
120 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
123 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
126 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
129 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
132 /* should not be reached! */
137 int board_early_init_f (void)
140 * First pull fpga-prg pin low, to disable fpga logic
142 out_be32((void*)GPIO0_ODR
, 0x00000000); /* no open drain pins */
143 out_be32((void*)GPIO0_TCR
, CONFIG_SYS_FPGA_PRG
); /* setup for output */
144 out_be32((void*)GPIO0_OR
, 0); /* pull prg low */
147 * IRQ 0-15 405GP internally generated; active high; level sensitive
148 * IRQ 16 405GP internally generated; active low; level sensitive
150 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
151 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
152 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
153 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
154 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
155 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
156 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
158 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
159 mtdcr(uicer
, 0x00000000); /* disable all ints */
160 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
161 mtdcr(uicpr
, 0xFFFFFF81); /* set int polarities */
162 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
163 mtdcr(uicvcr
, 0x00000001); /* set vect base=0 */
164 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
167 * EBC Configuration Register: set ready timeout to 512 ebc-clks
169 mtebc(epcr
, 0xa8400000); /* ebc always driven */
172 * New boards have a single 32MB flash connected to CS0
173 * instead of two 16MB flashes on CS0+1.
175 if (board_revision() >= 8) {
180 /* resize CS0 to 32MB */
181 mtebc(pb0ap
, CONFIG_SYS_EBC_PB0AP_HWREV8
);
182 mtebc(pb0cr
, CONFIG_SYS_EBC_PB0CR_HWREV8
);
188 int board_early_init_r(void)
190 if (gd
->board_type
>= 8)
196 #define FUJI_BASE 0xf0100200
197 #define LCDBL_PWM 0xa0
198 #define LCDBL_PWMMIN 0xa4
199 #define LCDBL_PWMMAX 0xa8
201 int misc_init_r(void)
203 u16
*fpga_mode
= (u16
*)(CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
);
204 u16
*fpga_ctrl2
=(u16
*)(CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL2
);
205 u8
*duart0_mcr
= (u8
*)(DUART0_BA
+ 4);
206 u8
*duart1_mcr
= (u8
*)(DUART1_BA
+ 4);
208 ulong len
= sizeof(fpgadata
);
212 unsigned long cntrl0Reg
;
220 * Setup GPIO pins (CS6+CS7 as GPIO)
222 cntrl0Reg
= mfdcr(cntrl0
);
223 mtdcr(cntrl0
, cntrl0Reg
| 0x00300000);
225 dst
= malloc(CONFIG_SYS_FPGA_MAX_SIZE
);
226 if (gunzip(dst
, CONFIG_SYS_FPGA_MAX_SIZE
, (uchar
*)fpgadata
, &len
) != 0) {
227 printf("GUNZIP ERROR - must RESET board to recover\n");
228 do_reset(NULL
, 0, 0, NULL
);
231 status
= fpga_boot(dst
, len
);
233 printf("\nFPGA: Booting failed ");
235 case ERROR_FPGA_PRG_INIT_LOW
:
237 "INIT not low after asserting PROGRAM*)\n ");
239 case ERROR_FPGA_PRG_INIT_HIGH
:
241 "INIT not high after deasserting PROGRAM*)\n ");
243 case ERROR_FPGA_PRG_DONE
:
245 "DONE not high after programming FPGA)\n ");
249 /* display infos on fpgaimage */
251 for (i
= 0; i
< 4; i
++) {
253 printf("FPGA: %s\n", &(dst
[index
+1]));
258 for (i
= 20; i
> 0; i
--) {
259 printf("Rebooting in %2d seconds \r",i
);
260 for (index
= 0; index
< 1000; index
++)
264 do_reset(NULL
, 0, 0, NULL
);
267 /* restore gpio/cs settings */
268 mtdcr(cntrl0
, cntrl0Reg
);
272 /* display infos on fpgaimage */
274 for (i
= 0; i
< 4; i
++) {
276 printf("%s ", &(dst
[index
+ 1]));
284 * Reset FPGA via FPGA_DATA pin
286 SET_FPGA(FPGA_PRG
| FPGA_CLK
);
287 udelay(1000); /* wait 1ms */
288 SET_FPGA(FPGA_PRG
| FPGA_CLK
| FPGA_DATA
);
289 udelay(1000); /* wait 1ms */
292 * Write board revision in FPGA
295 (in_be16(fpga_ctrl2
) & 0xfff0) | (gd
->board_type
& 0x000f));
298 * Enable power on PS/2 interface (with reset)
300 out_be16(fpga_mode
, in_be16(fpga_mode
) | CONFIG_SYS_FPGA_CTRL_PS2_RESET
);
304 out_be16(fpga_mode
, in_be16(fpga_mode
) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET
);
307 * Enable interrupts in exar duart mcr[3]
309 out_8(duart0_mcr
, 0x08);
310 out_8(duart1_mcr
, 0x08);
313 * Init lcd interface and display logo
315 str
= getenv("splashimage");
317 logo_addr
= (uchar
*)simple_strtoul(str
, NULL
, 16);
318 logo_size
= CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
;
320 logo_addr
= logo_bmp
;
321 logo_size
= sizeof(logo_bmp
);
324 if (gd
->board_type
>= 6) {
325 result
= lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
,
326 (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
327 regs_13505_640_480_16bpp
,
328 sizeof(regs_13505_640_480_16bpp
) /
329 sizeof(regs_13505_640_480_16bpp
[0]),
330 logo_addr
, logo_size
);
332 /* retry with internal image */
333 logo_addr
= logo_bmp
;
334 logo_size
= sizeof(logo_bmp
);
335 lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
,
336 (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
337 regs_13505_640_480_16bpp
,
338 sizeof(regs_13505_640_480_16bpp
) /
339 sizeof(regs_13505_640_480_16bpp
[0]),
340 logo_addr
, logo_size
);
343 result
= lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
,
344 (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
345 regs_13806_640_480_16bpp
,
346 sizeof(regs_13806_640_480_16bpp
) /
347 sizeof(regs_13806_640_480_16bpp
[0]),
348 logo_addr
, logo_size
);
350 /* retry with internal image */
351 logo_addr
= logo_bmp
;
352 logo_size
= sizeof(logo_bmp
);
353 lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
,
354 (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
355 regs_13806_640_480_16bpp
,
356 sizeof(regs_13806_640_480_16bpp
) /
357 sizeof(regs_13806_640_480_16bpp
[0]),
358 logo_addr
, logo_size
);
363 * Reset microcontroller and setup backlight PWM controller
365 out_be16(fpga_mode
, in_be16(fpga_mode
) | 0x0014);
368 out_be16(fpga_mode
, in_be16(fpga_mode
) | 0x001c);
372 str
= getenv("lcdbl");
374 minb
= (ushort
)simple_strtoul(str
, &str
, 16) & 0x00ff;
375 if (str
&& (*str
=',')) {
377 maxb
= (ushort
)simple_strtoul(str
, NULL
, 16) & 0x00ff;
381 out_be16((u16
*)(FUJI_BASE
+ LCDBL_PWMMIN
), minb
);
382 out_be16((u16
*)(FUJI_BASE
+ LCDBL_PWMMAX
), maxb
);
384 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb
, maxb
);
386 out_be16((u16
*)(FUJI_BASE
+ LCDBL_PWM
), 0xff);
389 * fix environment for field updated units
391 if (getenv("altbootcmd") == NULL
) {
392 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND
);
393 setenv("usbargs", CONFIG_SYS_USB_ARGS
);
394 setenv("bootcmd", CONFIG_BOOTCOMMAND
);
395 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND
);
396 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT
);
397 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND
);
405 * Check Board Identity:
407 int checkboard (void)
410 int i
= getenv_r ("serial#", str
, sizeof(str
));
415 puts ("### No HW ID - assuming APC405");
420 gd
->board_type
= board_revision();
421 printf(", Rev. 1.%ld\n", gd
->board_type
);
426 #ifdef CONFIG_IDE_RESET
427 void ide_set_reset(int on
)
429 u16
*fpga_mode
= (u16
*)(CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
);
432 * Assert or deassert CompactFlash Reset Pin
436 in_be16(fpga_mode
) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET
);
439 in_be16(fpga_mode
) | CONFIG_SYS_FPGA_CTRL_CF_RESET
);
442 #endif /* CONFIG_IDE_RESET */
447 * Disable sleep mode in LXT971
452 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
453 int usb_board_init(void)
458 int usb_board_stop(void)
465 * This is required to make some very old Linux OHCI driver
466 * work after U-Boot has used the OHCI controller.
468 pci_read_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, &tmp
);
469 pci_write_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, (tmp
| 0x1000));
471 for (i
= 0; i
< 100; i
++)
474 pci_write_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, tmp
);
478 int usb_board_init_fail(void)
483 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */