]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/esd/cpci2dp/cpci2dp.c
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / esd / cpci2dp / cpci2dp.c
1 /*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <asm/processor.h>
26 #include <command.h>
27 #include <malloc.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 int board_early_init_f (void)
32 {
33 unsigned long cntrl0Reg;
34
35 /*
36 * Setup GPIO pins
37 */
38 cntrl0Reg = mfdcr(cntrl0);
39 mtdcr(cntrl0, cntrl0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
40
41 /* set output pins to high */
42 out32(GPIO0_OR, CONFIG_SYS_EEPROM_WP);
43 /* setup for output (LED=off) */
44 out32(GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
45
46 /*
47 * IRQ 0-15 405GP internally generated; active high; level sensitive
48 * IRQ 16 405GP internally generated; active low; level sensitive
49 * IRQ 17-24 RESERVED
50 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
51 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
52 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
53 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
54 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
55 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
56 * IRQ 31 (EXT IRQ 6) unused
57 */
58 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
59 mtdcr(uicer, 0x00000000); /* disable all ints */
60 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
61 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
62
63 mtdcr(uictr, 0x10000000); /* set int trigger levels */
64 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
65 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
66
67 return 0;
68 }
69
70 int misc_init_r (void)
71 {
72 unsigned long cntrl0Reg;
73
74 /* adjust flash start and offset */
75 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
76 gd->bd->bi_flashoffset = 0;
77
78 /*
79 * Select cts (and not dsr) on uart1
80 */
81 cntrl0Reg = mfdcr(cntrl0);
82 mtdcr(cntrl0, cntrl0Reg | 0x00001000);
83
84 return (0);
85 }
86
87
88 /*
89 * Check Board Identity:
90 */
91 int checkboard (void)
92 {
93 char str[64];
94 int i = getenv_r ("serial#", str, sizeof(str));
95
96 puts ("Board: ");
97
98 if (i == -1) {
99 puts ("### No HW ID - assuming CPCI2DP");
100 } else {
101 puts(str);
102 }
103
104 printf(" (Ver 1.0)");
105
106 putc ('\n');
107
108 return 0;
109 }
110
111 #if defined(CONFIG_SYS_EEPROM_WREN)
112 /* Input: <dev_addr> I2C address of EEPROM device to enable.
113 * <state> -1: deliver current state
114 * 0: disable write
115 * 1: enable write
116 * Returns: -1: wrong device address
117 * 0: dis-/en- able done
118 * 0/1: current state if <state> was -1.
119 */
120 int eeprom_write_enable (unsigned dev_addr, int state) {
121 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
122 return -1;
123 } else {
124 switch (state) {
125 case 1:
126 /* Enable write access, clear bit GPIO_SINT2. */
127 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
128 state = 0;
129 break;
130 case 0:
131 /* Disable write access, set bit GPIO_SINT2. */
132 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
133 state = 0;
134 break;
135 default:
136 /* Read current status back. */
137 state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
138 break;
139 }
140 }
141 return state;
142 }
143 #endif
144
145 #if defined(CONFIG_SYS_EEPROM_WREN)
146 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
147 {
148 int query = argc == 1;
149 int state = 0;
150
151 if (query) {
152 /* Query write access state. */
153 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
154 if (state < 0) {
155 puts ("Query of write access state failed.\n");
156 } else {
157 printf ("Write access for device 0x%0x is %sabled.\n",
158 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
159 state = 0;
160 }
161 } else {
162 if ('0' == argv[1][0]) {
163 /* Disable write access. */
164 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
165 } else {
166 /* Enable write access. */
167 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
168 }
169 if (state < 0) {
170 puts ("Setup of write access state failed.\n");
171 }
172 }
173
174 return state;
175 }
176
177 U_BOOT_CMD(
178 eepwren, 2, 0, do_eep_wren,
179 "eepwren - Enable / disable / query EEPROM write access\n",
180 NULL
181 );
182 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */