2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * (C) Copyright 2006-2007
9 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
37 DECLARE_GLOBAL_DATA_PTR
;
39 #ifdef CONFIG_VIDEO_SM501
41 #define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
42 (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
44 #ifdef CONFIG_VIDEO_SM501_8BPP
45 #error CONFIG_VIDEO_SM501_8BPP not supported.
46 #endif /* CONFIG_VIDEO_SM501_8BPP */
48 #ifdef CONFIG_VIDEO_SM501_16BPP
52 * 800x600 display B084SN03: PCLK = 40MHz
57 static const SMI_REGS init_regs_800x600
[] =
60 {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
62 {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
64 {0x00004, SWAP32(0x00000000)},
65 /* clocks for pm1... */
66 {0x00048, SWAP32(0x00021807)},
67 {0x0004C, SWAP32(0x221a0a01)},
68 {0x00054, SWAP32(0x00000001)},
69 /* clocks for pm0... */
70 {0x00040, SWAP32(0x00021807)},
71 {0x00044, SWAP32(0x221a0a01)},
72 {0x00054, SWAP32(0x00000000)},
74 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
75 /* panel control regs... */
76 {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
77 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
78 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
79 {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
80 {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
81 {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
82 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
83 {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
84 {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
85 {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
86 {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
87 {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
88 {0x80200, SWAP32(0x00010000)}, /* crt display control */
93 * 1024x768 display G150XG02: PCLK = 65MHz
98 static const SMI_REGS init_regs_1024x768
[] =
100 {0x00004, SWAP32(0x00000000)},
101 /* clocks for pm1... */
102 {0x00048, SWAP32(0x00021807)},
103 {0x0004C, SWAP32(0x011a0a01)},
104 {0x00054, SWAP32(0x00000001)},
105 /* clocks for pm0... */
106 {0x00040, SWAP32(0x00021807)},
107 {0x00044, SWAP32(0x011a0a01)},
108 {0x00054, SWAP32(0x00000000)},
110 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
111 /* panel control regs... */
112 {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
113 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
114 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
115 {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
116 {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
117 {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
118 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
119 {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
120 {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
121 {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
122 {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
123 {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
124 {0x80200, SWAP32(0x00010000)}, /* crt display control */
128 #endif /* CONFIG_VIDEO_SM501_16BPP */
130 #ifdef CONFIG_VIDEO_SM501_32BPP
134 * 800x600 display B084SN03: PCLK = 40MHz
139 static const SMI_REGS init_regs_800x600
[] =
141 #if 0 /* test-only */
142 {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
144 {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
146 {0x00004, SWAP32(0x00000000)},
147 /* clocks for pm1... */
148 {0x00048, SWAP32(0x00021807)},
149 {0x0004C, SWAP32(0x221a0a01)},
150 {0x00054, SWAP32(0x00000001)},
151 /* clocks for pm0... */
152 {0x00040, SWAP32(0x00021807)},
153 {0x00044, SWAP32(0x221a0a01)},
154 {0x00054, SWAP32(0x00000000)},
156 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
157 /* panel control regs... */
158 {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
159 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
160 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
161 {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
162 {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
163 {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
164 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
165 {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
166 {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
167 {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
168 {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
169 {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
170 {0x80200, SWAP32(0x00010000)}, /* crt display control */
175 * 1024x768 display G150XG02: PCLK = 65MHz
180 static const SMI_REGS init_regs_1024x768
[] =
182 {0x00004, SWAP32(0x00000000)},
183 /* clocks for pm1... */
184 {0x00048, SWAP32(0x00021807)},
185 {0x0004C, SWAP32(0x011a0a01)},
186 {0x00054, SWAP32(0x00000001)},
187 /* clocks for pm0... */
188 {0x00040, SWAP32(0x00021807)},
189 {0x00044, SWAP32(0x011a0a01)},
190 {0x00054, SWAP32(0x00000000)},
192 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
193 /* panel control regs... */
194 {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
195 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
196 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
197 {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
198 {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
199 {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
200 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
201 {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
202 {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
203 {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
204 {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
205 {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
206 {0x80200, SWAP32(0x00010000)}, /* crt display control */
210 #endif /* CONFIG_VIDEO_SM501_32BPP */
212 #endif /* CONFIG_VIDEO_SM501 */
218 extern int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]);
219 extern void lxt971_no_sleep(void);
221 /* fpga configuration data - gzip compressed and generated by bin2c */
222 const unsigned char fpgadata
[] =
224 #include "fpgadata.c"
228 * include common fpga code (for esd boards)
230 #include "../common/fpga.c"
234 int gunzip(void *, int, unsigned char *, unsigned long *);
237 /* logo bitmap data - gzip compressed and generated by bin2c */
238 unsigned char logo_bmp_320
[] =
240 #include "logo_320_240_4bpp.c"
243 unsigned char logo_bmp_320_8bpp
[] =
245 #include "logo_320_240_8bpp.c"
248 unsigned char logo_bmp_640
[] =
250 #include "logo_640_480_24bpp.c"
253 unsigned char logo_bmp_1024
[] =
255 #include "logo_1024_768_8bpp.c"
260 * include common lcd code (for esd boards)
262 #include "../common/lcd.c"
264 #include "../common/s1d13704_320_240_4bpp.h"
265 #include "../common/s1d13705_320_240_8bpp.h"
266 #include "../common/s1d13806_640_480_16bpp.h"
267 #include "../common/s1d13806_1024_768_8bpp.h"
271 * include common auto-update code (for esd boards)
273 #include "../common/auto_update.h"
275 au_image_t au_image
[] = {
276 {"hh405/preinst.img", 0, -1, AU_SCRIPT
},
277 {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE
},
278 {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND
},
279 {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND
},
280 {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND
},
281 {"hh405/postinst.img", 0, 0, AU_SCRIPT
},
284 int N_AU_IMAGES
= (sizeof(au_image
) / sizeof(au_image
[0]));
288 * Get version of HH405 board from GPIO's
290 int board_revision(void)
292 unsigned long osrh_reg
;
293 unsigned long isr1h_reg
;
294 unsigned long tcr_reg
;
298 * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
300 osrh_reg
= in32(GPIO0_OSRH
);
301 isr1h_reg
= in32(GPIO0_ISR1H
);
302 tcr_reg
= in32(GPIO0_TCR
);
303 out32(GPIO0_OSRH
, osrh_reg
& ~0xC0003000); /* output select */
304 out32(GPIO0_ISR1H
, isr1h_reg
| 0xC0003000); /* input select */
305 out32(GPIO0_TCR
, tcr_reg
& ~0x80400000); /* select input */
307 udelay(1000); /* wait some time before reading input */
308 value
= in32(GPIO0_IR
) & 0x80400000; /* get config bits */
311 * Restore GPIO settings
313 out32(GPIO0_OSRH
, osrh_reg
); /* output select */
314 out32(GPIO0_ISR1H
, isr1h_reg
); /* input select */
315 out32(GPIO0_TCR
, tcr_reg
); /* enable output driver for outputs */
317 if (value
& 0x80000000) {
318 /* Revision 1.0 or 1.1 detected */
321 if (value
& 0x00400000) {
331 int board_early_init_f (void)
334 * IRQ 0-15 405GP internally generated; active high; level sensitive
335 * IRQ 16 405GP internally generated; active low; level sensitive
337 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
338 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
339 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
340 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
341 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
342 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
343 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
345 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
346 mtdcr(uicer
, 0x00000000); /* disable all ints */
347 mtdcr(uiccr
, 0x00000000); /* set all to be non-critical*/
348 mtdcr(uicpr
, CONFIG_SYS_UIC0_POLARITY
);/* set int polarities */
349 mtdcr(uictr
, 0x10000000); /* set int trigger levels */
350 mtdcr(uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority*/
351 mtdcr(uicsr
, 0xFFFFFFFF); /* clear all ints */
354 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
356 mtebc (epcr
, 0xa8400000); /* ebc always driven */
365 volatile unsigned short *fpga_ctrl
=
366 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
);
367 volatile unsigned short *fpga_status
=
368 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
+ 2);
370 if (gd
->board_type
>= 2) {
371 if (*fpga_status
& CONFIG_SYS_FPGA_STATUS_CF_DETECT
) {
372 if (!(*fpga_ctrl
& CONFIG_SYS_FPGA_CTRL_CF_BUS_EN
)) {
373 *fpga_ctrl
&= ~CONFIG_SYS_FPGA_CTRL_CF_PWRN
;
375 for (i
=0; i
<300; i
++)
378 *fpga_ctrl
|= CONFIG_SYS_FPGA_CTRL_CF_BUS_EN
;
384 *fpga_ctrl
&= ~CONFIG_SYS_FPGA_CTRL_CF_BUS_EN
;
385 *fpga_ctrl
|= CONFIG_SYS_FPGA_CTRL_CF_PWRN
;
392 int misc_init_r (void)
394 volatile unsigned short *fpga_ctrl
=
395 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
);
396 volatile unsigned short *lcd_contrast
=
397 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
+ 4);
398 volatile unsigned short *lcd_backlight
=
399 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
+ 6);
401 ulong len
= sizeof(fpgadata
);
406 unsigned long contrast0
= 0xffffffff;
408 dst
= malloc(CONFIG_SYS_FPGA_MAX_SIZE
);
409 if (gunzip (dst
, CONFIG_SYS_FPGA_MAX_SIZE
, (uchar
*)fpgadata
, &len
) != 0) {
410 printf ("GUNZIP ERROR - must RESET board to recover\n");
411 do_reset (NULL
, 0, 0, NULL
);
414 status
= fpga_boot(dst
, len
);
416 printf("\nFPGA: Booting failed ");
418 case ERROR_FPGA_PRG_INIT_LOW
:
419 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
421 case ERROR_FPGA_PRG_INIT_HIGH
:
422 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
424 case ERROR_FPGA_PRG_DONE
:
425 printf("(Timeout: DONE not high after programming FPGA)\n ");
429 /* display infos on fpgaimage */
431 for (i
=0; i
<4; i
++) {
433 printf("FPGA: %s\n", &(dst
[index
+1]));
438 for (i
=20; i
>0; i
--) {
439 printf("Rebooting in %2d seconds \r",i
);
440 for (index
=0;index
<1000;index
++)
444 do_reset(NULL
, 0, 0, NULL
);
449 /* display infos on fpgaimage */
451 for (i
=0; i
<4; i
++) {
453 printf("%s ", &(dst
[index
+1]));
461 * Reset FPGA via FPGA_INIT pin
463 out32(GPIO0_TCR
, in32(GPIO0_TCR
) | FPGA_INIT
); /* setup FPGA_INIT as output */
464 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~FPGA_INIT
); /* reset low */
465 udelay(1000); /* wait 1ms */
466 out32(GPIO0_OR
, in32(GPIO0_OR
) | FPGA_INIT
); /* reset high */
467 udelay(1000); /* wait 1ms */
470 * Write Board revision into FPGA
472 *fpga_ctrl
|= gd
->board_type
& 0x0003;
475 * Setup and enable EEPROM write protection
477 out32(GPIO0_OR
, in32(GPIO0_OR
) | CONFIG_SYS_EEPROM_WP
);
480 * Reset touch-screen controller
482 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~CONFIG_SYS_TOUCH_RST
);
484 out32(GPIO0_OR
, in32(GPIO0_OR
) | CONFIG_SYS_TOUCH_RST
);
487 * Enable power on PS/2 interface (with reset)
489 *fpga_ctrl
&= ~(CONFIG_SYS_FPGA_CTRL_PS2_PWR
);
492 *fpga_ctrl
|= (CONFIG_SYS_FPGA_CTRL_PS2_PWR
);
495 * Get contrast value from environment variable
497 str
= getenv("contrast0");
499 contrast0
= simple_strtol(str
, NULL
, 16);
500 if (contrast0
> 255) {
501 printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0
);
502 contrast0
= 0xffffffff;
507 * Init lcd interface and display logo
510 str
= getenv("bd_type");
511 if (strcmp(str
, "ppc230") == 0) {
513 * Switch backlight on
515 *fpga_ctrl
|= CONFIG_SYS_FPGA_CTRL_VGA0_BL
;
516 *lcd_backlight
= 0x0000;
519 lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
, (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
520 regs_13806_1024_768_8bpp
,
521 sizeof(regs_13806_1024_768_8bpp
)/sizeof(regs_13806_1024_768_8bpp
[0]),
522 logo_bmp_1024
, sizeof(logo_bmp_1024
));
523 } else if (strcmp(str
, "ppc220") == 0) {
525 * Switch backlight on
527 *fpga_ctrl
&= ~CONFIG_SYS_FPGA_CTRL_VGA0_BL
;
528 *lcd_backlight
= 0x0000;
531 lcd_init((uchar
*)CONFIG_SYS_LCD_BIG_REG
, (uchar
*)CONFIG_SYS_LCD_BIG_MEM
,
532 regs_13806_640_480_16bpp
,
533 sizeof(regs_13806_640_480_16bpp
)/sizeof(regs_13806_640_480_16bpp
[0]),
534 logo_bmp_640
, sizeof(logo_bmp_640
));
535 } else if (strcmp(str
, "ppc215") == 0) {
537 * Set default display contrast voltage
539 if (contrast0
== 0xffffffff) {
540 *lcd_contrast
= 0x0082;
542 *lcd_contrast
= contrast0
;
544 *lcd_backlight
= 0xffff;
546 * Switch backlight on
548 *fpga_ctrl
|= CONFIG_SYS_FPGA_CTRL_VGA0_BL
| CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE
;
550 * Set lcd clock (small epson)
552 *fpga_ctrl
|= LCD_CLK_06250
;
553 udelay(100); /* wait for 100 us */
556 lcd_init((uchar
*)CONFIG_SYS_LCD_SMALL_REG
, (uchar
*)CONFIG_SYS_LCD_SMALL_MEM
,
557 regs_13705_320_240_8bpp
,
558 sizeof(regs_13705_320_240_8bpp
)/sizeof(regs_13705_320_240_8bpp
[0]),
559 logo_bmp_320_8bpp
, sizeof(logo_bmp_320_8bpp
));
560 } else if (strcmp(str
, "ppc210") == 0) {
562 * Set default display contrast voltage
564 if (contrast0
== 0xffffffff) {
565 *lcd_contrast
= 0x0060;
567 *lcd_contrast
= contrast0
;
569 *lcd_backlight
= 0xffff;
571 * Switch backlight on
573 *fpga_ctrl
|= CONFIG_SYS_FPGA_CTRL_VGA0_BL
| CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE
;
575 * Set lcd clock (small epson), enable 1-wire interface
577 *fpga_ctrl
|= LCD_CLK_08330
| CONFIG_SYS_FPGA_CTRL_OW_ENABLE
;
580 lcd_init((uchar
*)CONFIG_SYS_LCD_SMALL_REG
, (uchar
*)CONFIG_SYS_LCD_SMALL_MEM
,
581 regs_13704_320_240_4bpp
,
582 sizeof(regs_13704_320_240_4bpp
)/sizeof(regs_13704_320_240_4bpp
[0]),
583 logo_bmp_320
, sizeof(logo_bmp_320
));
584 #ifdef CONFIG_VIDEO_SM501
589 * Is SM501 connected (ppc221/ppc231)?
591 devbusfn
= pci_find_device(PCI_VENDOR_SM
, PCI_DEVICE_SM501
, 0);
592 if (devbusfn
!= -1) {
593 puts("VGA: SM501 with 8 MB ");
594 if (strcmp(str
, "ppc221") == 0) {
595 printf("(800*600, %dbpp)\n", BPP
);
596 *lcd_backlight
= 0x002d; /* max. allowed brightness */
597 } else if (strcmp(str
, "ppc231") == 0) {
598 printf("(1024*768, %dbpp)\n", BPP
);
599 *lcd_backlight
= 0x0000;
601 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str
);
605 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str
);
608 #endif /* CONFIG_VIDEO_SM501 */
618 * Check Board Identity:
621 int checkboard (void)
624 int i
= getenv_r ("serial#", str
, sizeof(str
));
629 puts ("### No HW ID - assuming HH405");
634 if (getenv_r("bd_type", str
, sizeof(str
)) != -1) {
637 puts(" (Missing bd_type!");
640 gd
->board_type
= board_revision();
641 printf(", Rev %ld.x)\n", gd
->board_type
);
646 #ifdef CONFIG_IDE_RESET
647 void ide_set_reset(int on
)
649 volatile unsigned short *fpga_mode
=
650 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
);
651 volatile unsigned short *fpga_status
=
652 (unsigned short *)((ulong
)CONFIG_SYS_FPGA_BASE_ADDR
+ CONFIG_SYS_FPGA_CTRL
+ 2);
654 if (((gd
->board_type
>= 2) && (*fpga_status
& CONFIG_SYS_FPGA_STATUS_CF_DETECT
)) ||
655 (gd
->board_type
< 2)) {
657 * Assert or deassert CompactFlash Reset Pin
659 if (on
) { /* assert RESET */
661 *fpga_mode
&= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET
);
662 } else { /* release RESET */
663 *fpga_mode
|= CONFIG_SYS_FPGA_CTRL_CF_RESET
;
667 #endif /* CONFIG_IDE_RESET */
670 #if defined(CONFIG_SYS_EEPROM_WREN)
671 /* Input: <dev_addr> I2C address of EEPROM device to enable.
672 * <state> -1: deliver current state
675 * Returns: -1: wrong device address
676 * 0: dis-/en- able done
677 * 0/1: current state if <state> was -1.
679 int eeprom_write_enable (unsigned dev_addr
, int state
)
681 if (CONFIG_SYS_I2C_EEPROM_ADDR
!= dev_addr
) {
686 /* Enable write access, clear bit GPIO_SINT2. */
687 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~CONFIG_SYS_EEPROM_WP
);
691 /* Disable write access, set bit GPIO_SINT2. */
692 out32(GPIO0_OR
, in32(GPIO0_OR
) | CONFIG_SYS_EEPROM_WP
);
696 /* Read current status back. */
697 state
= (0 == (in32(GPIO0_OR
) & CONFIG_SYS_EEPROM_WP
));
704 int do_eep_wren (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
706 int query
= argc
== 1;
710 /* Query write access state. */
711 state
= eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR
, -1);
713 puts ("Query of write access state failed.\n");
715 printf ("Write access for device 0x%0x is %sabled.\n",
716 CONFIG_SYS_I2C_EEPROM_ADDR
, state
? "en" : "dis");
720 if ('0' == argv
[1][0]) {
721 /* Disable write access. */
722 state
= eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR
, 0);
724 /* Enable write access. */
725 state
= eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR
, 1);
728 puts ("Setup of write access state failed.\n");
735 U_BOOT_CMD(eepwren
, 2, 0, do_eep_wren
,
736 "eepwren - Enable / disable / query EEPROM write access\n",
738 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
741 #ifdef CONFIG_VIDEO_SM501
742 #ifdef CONFIG_CONSOLE_EXTRA_INFO
744 * Return text to be printed besides the logo.
746 void video_get_info_str (int line_number
, char *info
)
750 int i
= getenv_r("serial#", str2
, sizeof(str
));
752 if (line_number
== 1) {
753 sprintf(str
, " Board: ");
756 strcat(str
, "### No HW ID - assuming HH405");
761 if (getenv_r("bd_type", str2
, sizeof(str2
)) != -1) {
765 strcat(str
, " (Missing bd_type!");
768 sprintf(str2
, ", Rev %ld.x)", gd
->board_type
);
775 #endif /* CONFIG_CONSOLE_EXTRA_INFO */
778 * Returns SM501 register base address. First thing called in the driver.
780 unsigned int board_video_init (void)
786 * Is SM501 connected (ppc221/ppc231)?
788 devbusfn
= pci_find_device(PCI_VENDOR_SM
, PCI_DEVICE_SM501
, 0);
789 if (devbusfn
!= -1) {
790 pci_read_config_dword(devbusfn
, PCI_BASE_ADDRESS_1
, (u32
*)&addr
);
791 return (addr
& 0xfffffffe);
798 * Returns SM501 framebuffer address
800 unsigned int board_video_get_fb (void)
806 * Is SM501 connected (ppc221/ppc231)?
808 devbusfn
= pci_find_device(PCI_VENDOR_SM
, PCI_DEVICE_SM501
, 0);
809 if (devbusfn
!= -1) {
810 pci_read_config_dword(devbusfn
, PCI_BASE_ADDRESS_0
, (u32
*)&addr
);
812 #ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
813 addr
+= CONFIG_VIDEO_SM501_FBMEM_OFFSET
;
822 * Called after initializing the SM501 and before clearing the screen.
824 void board_validate_screen (unsigned int base
)
829 * Return a pointer to the initialization sequence.
831 const SMI_REGS
*board_get_regs (void)
835 str
= getenv("bd_type");
836 if (strcmp(str
, "ppc221") == 0) {
837 return init_regs_800x600
;
839 return init_regs_1024x768
;
843 int board_get_width (void)
847 str
= getenv("bd_type");
848 if (strcmp(str
, "ppc221") == 0) {
855 int board_get_height (void)
859 str
= getenv("bd_type");
860 if (strcmp(str
, "ppc221") == 0) {
867 #endif /* CONFIG_VIDEO_SM501 */
872 #ifdef CONFIG_LXT971_NO_SLEEP
875 * Disable sleep mode in LXT971