2 * (C) Copyright 2007-2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on board/amcc/sequoia/sequoia.c
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <fdt_support.h>
33 #include <asm/processor.h>
35 #include <asm/bitops.h>
38 #ifdef CONFIG_RESET_PHY_R
45 DECLARE_GLOBAL_DATA_PTR
;
47 extern flash_info_t flash_info
[CONFIG_SYS_MAX_FLASH_BANKS
]; /* info for FLASH chips */
49 ulong
flash_get_size(ulong base
, int banknum
);
50 int pci_is_66mhz(void);
51 int bootstrap_eeprom_read(unsigned dev_addr
, unsigned offset
,
52 uchar
*buffer
, unsigned cnt
);
54 struct serial_device
*default_serial_console(void)
62 * Use default console on P4 when strapping jumper
63 * is installed (bootstrap option != 'H').
65 mfsdr(SDR_PINSTP
, val
);
66 if (((val
& 0xf0000000) >> 29) != 7)
67 return &serial1_device
;
69 ulong scratchreg
= in_be32((void*)GPIO0_ISR3L
);
70 if (!(scratchreg
& 0x80)) {
71 /* mark scratchreg valid */
72 scratchreg
= (scratchreg
& 0xffffff00) | 0x80;
74 i
= bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR
,
76 if ((i
!= -1) && (buf
[0] == 0x19) && (buf
[1] == 0x75)) {
79 /* bringup delay for console */
80 for (delay
=0; delay
<(1000 * (ulong
)buf
[3]); delay
++) {
85 out_be32((void*)GPIO0_ISR3L
, scratchreg
);
88 if (scratchreg
& 0x01)
89 return &serial1_device
;
91 return &serial0_device
;
94 int board_early_init_f(void)
97 u32 sdr0_pfc1
, sdr0_pfc2
;
100 /* general EBC configuration (disable EBC timeouts) */
101 mtdcr(ebccfga
, xbcfg
);
102 mtdcr(ebccfgd
, 0xf8400000);
105 * Setup the GPIO pins
106 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
108 out32(GPIO0_OR
, 0x40000002);
109 out32(GPIO0_TCR
, 0x4c90011f);
110 out32(GPIO0_OSRL
, 0x28011400);
111 out32(GPIO0_OSRH
, 0x55005000);
112 out32(GPIO0_TSRL
, 0x08011400);
113 out32(GPIO0_TSRH
, 0x55005000);
114 out32(GPIO0_ISR1L
, 0x54000000);
115 out32(GPIO0_ISR1H
, 0x00000000);
116 out32(GPIO0_ISR2L
, 0x44000000);
117 out32(GPIO0_ISR2H
, 0x00000100);
118 out32(GPIO0_ISR3L
, 0x00000000);
119 out32(GPIO0_ISR3H
, 0x00000000);
121 out32(GPIO1_OR
, 0x80002408);
122 out32(GPIO1_TCR
, 0xd6003c08);
123 out32(GPIO1_OSRL
, 0x0a5a0000);
124 out32(GPIO1_OSRH
, 0x00000000);
125 out32(GPIO1_TSRL
, 0x00000000);
126 out32(GPIO1_TSRH
, 0x00000000);
127 out32(GPIO1_ISR1L
, 0x00005555);
128 out32(GPIO1_ISR1H
, 0x40000000);
129 out32(GPIO1_ISR2L
, 0x04010000);
130 out32(GPIO1_ISR2H
, 0x00000000);
131 out32(GPIO1_ISR3L
, 0x01400000);
132 out32(GPIO1_ISR3H
, 0x00000000);
134 /* patch PLB:PCI divider for 66MHz PCI */
135 mfcpr(clk_spcid
, reg
);
136 if (pci_is_66mhz() && (reg
!= 0x02000000)) {
137 mtcpr(clk_spcid
, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
139 mfcpr(clk_icfg
, reg
);
140 reg
|= CPR0_ICFG_RLI_MASK
;
141 mtcpr(clk_icfg
, reg
);
143 mtspr(dbcr0
, 0x20000000); /* do chip reset */
147 * Setup the interrupt controller polarities, triggers, etc.
149 mtdcr(uic0sr
, 0xffffffff); /* clear all */
150 mtdcr(uic0er
, 0x00000000); /* disable all */
151 mtdcr(uic0cr
, 0x00000005); /* ATI & UIC1 crit are critical */
152 mtdcr(uic0pr
, 0xfffff7ef);
153 mtdcr(uic0tr
, 0x00000000);
154 mtdcr(uic0vr
, 0x00000000); /* int31 highest, base=0x000 */
155 mtdcr(uic0sr
, 0xffffffff); /* clear all */
157 mtdcr(uic1sr
, 0xffffffff); /* clear all */
158 mtdcr(uic1er
, 0x00000000); /* disable all */
159 mtdcr(uic1cr
, 0x00000000); /* all non-critical */
160 mtdcr(uic1pr
, 0xffffc7f5);
161 mtdcr(uic1tr
, 0x00000000);
162 mtdcr(uic1vr
, 0x00000000); /* int31 highest, base=0x000 */
163 mtdcr(uic1sr
, 0xffffffff); /* clear all */
165 mtdcr(uic2sr
, 0xffffffff); /* clear all */
166 mtdcr(uic2er
, 0x00000000); /* disable all */
167 mtdcr(uic2cr
, 0x00000000); /* all non-critical */
168 mtdcr(uic2pr
, 0x27ffffff);
169 mtdcr(uic2tr
, 0x00000000);
170 mtdcr(uic2vr
, 0x00000000); /* int31 highest, base=0x000 */
171 mtdcr(uic2sr
, 0xffffffff); /* clear all */
173 /* select Ethernet pins */
174 mfsdr(SDR0_PFC1
, sdr0_pfc1
);
175 sdr0_pfc1
= (sdr0_pfc1
& ~SDR0_PFC1_SELECT_MASK
) |
176 SDR0_PFC1_SELECT_CONFIG_4
;
177 mfsdr(SDR0_PFC2
, sdr0_pfc2
);
178 sdr0_pfc2
= (sdr0_pfc2
& ~SDR0_PFC2_SELECT_MASK
) |
179 SDR0_PFC2_SELECT_CONFIG_4
;
182 sdr0_pfc1
= (sdr0_pfc1
& ~SDR0_PFC1_SIS_MASK
) | SDR0_PFC1_SIS_IIC1_SEL
;
184 mtsdr(SDR0_PFC2
, sdr0_pfc2
);
185 mtsdr(SDR0_PFC1
, sdr0_pfc1
);
187 /* setup NAND FLASH */
188 mfsdr(SDR0_CUST0
, sdr0_cust0
);
189 sdr0_cust0
= SDR0_CUST0_MUX_NDFC_SEL
|
190 SDR0_CUST0_NDFC_ENABLE
|
191 SDR0_CUST0_NDFC_BW_8_BIT
|
192 SDR0_CUST0_NDFC_ARE_MASK
|
193 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS
));
194 mtsdr(SDR0_CUST0
, sdr0_cust0
);
202 int misc_init_r(void)
207 unsigned long usb2d0cr
= 0;
208 unsigned long usb2phy0cr
, usb2h0cr
= 0;
209 unsigned long sdr0_pfc1
;
210 char *act
= getenv("usbact");
216 /* Re-do sizing to get full correct info */
218 /* adjust flash start and offset */
219 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
220 gd
->bd
->bi_flashoffset
= 0;
222 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
223 mtdcr(ebccfga
, pb2cr
);
225 mtdcr(ebccfga
, pb0cr
);
227 pbcr
= mfdcr(ebccfgd
);
228 size_val
= ffs(gd
->bd
->bi_flashsize
) - 21;
229 pbcr
= (pbcr
& 0x0001ffff) | gd
->bd
->bi_flashstart
| (size_val
<< 17);
230 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
231 mtdcr(ebccfga
, pb2cr
);
233 mtdcr(ebccfga
, pb0cr
);
235 mtdcr(ebccfgd
, pbcr
);
238 * Re-check to get correct base address
240 flash_get_size(gd
->bd
->bi_flashstart
, 0);
242 #ifdef CONFIG_ENV_IS_IN_FLASH
243 /* Monitor protection ON by default */
244 (void)flash_protect(FLAG_PROTECT_SET
,
245 -CONFIG_SYS_MONITOR_LEN
,
249 /* Env protection ON by default */
250 (void)flash_protect(FLAG_PROTECT_SET
,
251 CONFIG_ENV_ADDR_REDUND
,
252 CONFIG_ENV_ADDR_REDUND
+ 2*CONFIG_ENV_SECT_SIZE
- 1,
259 if ((act
== NULL
|| strcmp(act
, "hostdev") == 0) &&
260 !(in_be32((void*)GPIO0_IR
) & GPIO0_USB_PRSNT
)){
262 mfsdr(SDR0_PFC1
, sdr0_pfc1
);
263 mfsdr(SDR0_USB2D0CR
, usb2d0cr
);
264 mfsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
265 mfsdr(SDR0_USB2H0CR
, usb2h0cr
);
267 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_XOCLK_MASK
;
268 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_XOCLK_EXTERNAL
;
269 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_WDINT_MASK
;
270 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ
;
271 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DVBUS_MASK
;
272 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DVBUS_PURDIS
;
273 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DWNSTR_MASK
;
274 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DWNSTR_HOST
;
275 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_UTMICN_MASK
;
276 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_UTMICN_HOST
;
279 * An 8-bit/60MHz interface is the only possible alternative
280 * when connecting the Device to the PHY
282 usb2h0cr
= usb2h0cr
&~SDR0_USB2H0CR_WDINT_MASK
;
283 usb2h0cr
= usb2h0cr
| SDR0_USB2H0CR_WDINT_16BIT_30MHZ
;
285 usb2d0cr
= usb2d0cr
&~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK
;
286 sdr0_pfc1
= sdr0_pfc1
&~SDR0_PFC1_UES_MASK
;
288 mtsdr(SDR0_PFC1
, sdr0_pfc1
);
289 mtsdr(SDR0_USB2D0CR
, usb2d0cr
);
290 mtsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
291 mtsdr(SDR0_USB2H0CR
, usb2h0cr
);
295 mtsdr(SDR0_SRST1
, 0x00000000);
297 mtsdr(SDR0_SRST0
, 0x00000000);
299 printf("USB: Host\n");
301 } else if ((strcmp(act
, "dev") == 0) ||
302 (in_be32((void*)GPIO0_IR
) & GPIO0_USB_PRSNT
)) {
303 mfsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
305 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_XOCLK_MASK
;
306 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_XOCLK_EXTERNAL
;
307 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DVBUS_MASK
;
308 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DVBUS_PURDIS
;
309 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DWNSTR_MASK
;
310 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DWNSTR_HOST
;
311 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_UTMICN_MASK
;
312 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_UTMICN_HOST
;
313 mtsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
316 mtsdr(SDR0_SRST1
, 0x672c6000);
319 mtsdr(SDR0_SRST0
, 0x00000080);
322 mtsdr(SDR0_SRST1
, 0x60206000);
324 *(unsigned int *)(0xe0000350) = 0x00000001;
327 mtsdr(SDR0_SRST1
, 0x60306000);
330 mfsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
331 mfsdr(SDR0_USB2H0CR
, usb2h0cr
);
332 mfsdr(SDR0_USB2D0CR
, usb2d0cr
);
333 mfsdr(SDR0_PFC1
, sdr0_pfc1
);
335 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_XOCLK_MASK
;
336 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_XOCLK_EXTERNAL
;
337 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_WDINT_MASK
;
338 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ
;
339 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DVBUS_MASK
;
340 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DVBUS_PUREN
;
341 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_DWNSTR_MASK
;
342 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DWNSTR_DEV
;
343 usb2phy0cr
= usb2phy0cr
&~SDR0_USB2PHY0CR_UTMICN_MASK
;
344 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_UTMICN_DEV
;
346 usb2h0cr
= usb2h0cr
&~SDR0_USB2H0CR_WDINT_MASK
;
347 usb2h0cr
= usb2h0cr
| SDR0_USB2H0CR_WDINT_8BIT_60MHZ
;
349 usb2d0cr
= usb2d0cr
&~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK
;
351 sdr0_pfc1
= sdr0_pfc1
&~SDR0_PFC1_UES_MASK
;
352 sdr0_pfc1
= sdr0_pfc1
| SDR0_PFC1_UES_EBCHR_SEL
;
354 mtsdr(SDR0_USB2H0CR
, usb2h0cr
);
355 mtsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
356 mtsdr(SDR0_USB2D0CR
, usb2d0cr
);
357 mtsdr(SDR0_PFC1
, sdr0_pfc1
);
361 mtsdr(SDR0_SRST1
, 0x00000000);
363 mtsdr(SDR0_SRST0
, 0x00000000);
365 printf("USB: Device\n");
369 * Clear PLB4A0_ACR[WRP]
370 * This fix will make the MAL burst disabling patch for the Linux
371 * EMAC driver obsolete.
373 reg
= mfdcr(plb4_acr
) & ~PLB4_ACR_WRP
;
374 mtdcr(plb4_acr
, reg
);
380 /* turn off POST LED */
381 out_be32((void*)GPIO1_OR
, in_be32((void*)GPIO1_OR
) & ~GPIO1_POST_N
);
382 /* turn on RUN LED */
383 out_be32((void*)GPIO0_OR
, in_be32((void*)GPIO0_OR
) & ~GPIO0_LED_RUN_N
);
389 if (in_be32((void*)GPIO1_IR
) & GPIO1_NONMONARCH
)
395 int pci_is_66mhz(void)
397 if (in_be32((void*)GPIO1_IR
) & GPIO1_M66EN
)
402 int board_revision(void)
404 return (int)((in_be32((void*)GPIO1_IR
) & GPIO1_HWID_MASK
) >> 4);
409 puts("Board: esd GmbH - PMC440");
411 gd
->board_type
= board_revision();
412 printf(", Rev 1.%ld, ", gd
->board_type
);
418 printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
423 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
425 * Assign interrupts to PCI devices. Some OSs rely on this.
427 void pmc440_pci_fixup_irq(struct pci_controller
*hose
, pci_dev_t dev
)
429 unsigned char int_line
[] = {IRQ_PCIC
, IRQ_PCID
, IRQ_PCIA
, IRQ_PCIB
};
431 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
,
432 int_line
[PCI_DEV(dev
) & 0x03]);
439 * This routine is called just prior to registering the hose and gives
440 * the board the opportunity to check things. Returning a value of zero
441 * indicates that things are bad & PCI initialization should be aborted.
443 * Different boards may wish to customize the pci controller structure
444 * (add regions, override default access routines, etc) or perform
445 * certain pre-initialization actions.
447 #if defined(CONFIG_PCI)
448 int pci_pre_init(struct pci_controller
*hose
)
453 * Set priority for all PLB3 devices to 0.
454 * Set PLB3 arbiter to fair mode.
456 mfsdr(sdr_amp1
, addr
);
457 mtsdr(sdr_amp1
, (addr
& 0x000000FF) | 0x0000FF00);
458 addr
= mfdcr(plb3_acr
);
459 mtdcr(plb3_acr
, addr
| 0x80000000);
462 * Set priority for all PLB4 devices to 0.
464 mfsdr(sdr_amp0
, addr
);
465 mtsdr(sdr_amp0
, (addr
& 0x000000FF) | 0x0000FF00);
466 addr
= mfdcr(plb4_acr
) | 0xa0000000; /* Was 0x8---- */
467 mtdcr(plb4_acr
, addr
);
470 * Set Nebula PLB4 arbiter to fair mode.
473 addr
= (mfdcr(plb0_acr
) & ~plb0_acr_ppm_mask
) | plb0_acr_ppm_fair
;
474 addr
= (addr
& ~plb0_acr_hbu_mask
) | plb0_acr_hbu_enabled
;
475 addr
= (addr
& ~plb0_acr_rdp_mask
) | plb0_acr_rdp_4deep
;
476 addr
= (addr
& ~plb0_acr_wrp_mask
) | plb0_acr_wrp_2deep
;
477 mtdcr(plb0_acr
, addr
);
480 addr
= (mfdcr(plb1_acr
) & ~plb1_acr_ppm_mask
) | plb1_acr_ppm_fair
;
481 addr
= (addr
& ~plb1_acr_hbu_mask
) | plb1_acr_hbu_enabled
;
482 addr
= (addr
& ~plb1_acr_rdp_mask
) | plb1_acr_rdp_4deep
;
483 addr
= (addr
& ~plb1_acr_wrp_mask
) | plb1_acr_wrp_2deep
;
484 mtdcr(plb1_acr
, addr
);
486 #ifdef CONFIG_PCI_PNP
487 hose
->fixup_irq
= pmc440_pci_fixup_irq
;
492 #endif /* defined(CONFIG_PCI) */
497 * The bootstrap configuration provides default settings for the pci
498 * inbound map (PIM). But the bootstrap config choices are limited and
499 * may not be sufficient for a given board.
501 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
502 void pci_target_init(struct pci_controller
*hose
)
504 char *ptmla_str
, *ptmms_str
;
507 * Set up Direct MMIO registers
510 * PowerPC440EPX PCI Master configuration.
511 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
512 * PLB address 0x80000000-0xBFFFFFFF
513 * ==> PCI address 0x80000000-0xBFFFFFFF
514 * Use byte reversed out routines to handle endianess.
515 * Make this region non-prefetchable.
517 out32r(PCIX0_PMM0MA
, 0x00000000); /* PMM0 Mask/Attribute */
518 /* - disabled b4 setting */
519 out32r(PCIX0_PMM0LA
, CONFIG_SYS_PCI_MEMBASE
); /* PMM0 Local Address */
520 out32r(PCIX0_PMM0PCILA
, CONFIG_SYS_PCI_MEMBASE
); /* PMM0 PCI Low Address */
521 out32r(PCIX0_PMM0PCIHA
, 0x00000000); /* PMM0 PCI High Address */
522 out32r(PCIX0_PMM0MA
, 0xc0000001); /* 1G + No prefetching, */
523 /* and enable region */
526 ptmla_str
= getenv("ptm1la");
527 ptmms_str
= getenv("ptm1ms");
528 if(NULL
!= ptmla_str
&& NULL
!= ptmms_str
) {
530 simple_strtoul(ptmms_str
, NULL
, 16));
532 simple_strtoul(ptmla_str
, NULL
, 16));
534 /* BAR1: default top 64MB of RAM */
535 out32r(PCIX0_PTM1MS
, 0xfc000001);
536 out32r(PCIX0_PTM1LA
, 0x0c000000);
539 /* BAR1: default: complete 256MB RAM */
540 out32r(PCIX0_PTM1MS
, 0xf0000001);
541 out32r(PCIX0_PTM1LA
, 0x00000000);
544 ptmla_str
= getenv("ptm2la"); /* Local Addr. Reg */
545 ptmms_str
= getenv("ptm2ms"); /* Memory Size/Attribute */
546 if(NULL
!= ptmla_str
&& NULL
!= ptmms_str
) {
547 out32r(PCIX0_PTM2MS
, simple_strtoul(ptmms_str
, NULL
, 16));
548 out32r(PCIX0_PTM2LA
, simple_strtoul(ptmla_str
, NULL
, 16));
550 /* BAR2: default: 16 MB FPGA + registers */
551 out32r(PCIX0_PTM2MS
, 0xff000001); /* Memory Size/Attribute */
552 out32r(PCIX0_PTM2LA
, 0xef000000); /* Local Addr. Reg */
556 /* BAR2: map FPGA registers behind system memory at 1GB */
557 pci_write_config_dword(0, PCI_BASE_ADDRESS_2
, 0x40000008);
561 * Set up Configuration registers
564 /* Program the board's vendor id */
565 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID
,
566 CONFIG_SYS_PCI_SUBSYS_VENDORID
);
568 /* disabled for PMC405 backward compatibility */
569 /* Configure command register as bus master */
570 /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
573 /* 240nS PCI clock */
574 pci_write_config_word(0, PCI_LATENCY_TIMER
, 1);
576 /* No error reporting */
577 pci_write_config_word(0, PCI_ERREN
, 0);
579 pci_write_config_dword(0, PCI_BRDGOPT2
, 0x00000101);
582 /* Program the board's subsystem id/classcode */
583 pci_write_config_word(0, PCI_SUBSYSTEM_ID
,
584 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH
);
585 pci_write_config_word(0, PCI_CLASS_SUB_CODE
,
586 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH
);
588 /* PCI configuration done: release ERREADY */
589 out_be32((void*)GPIO1_OR
,
590 in_be32((void*)GPIO1_OR
) | GPIO1_PPC_EREADY
);
591 out_be32((void*)GPIO1_TCR
,
592 in_be32((void*)GPIO1_TCR
) | GPIO1_PPC_EREADY
);
594 /* Program the board's subsystem id/classcode */
595 pci_write_config_word(0, PCI_SUBSYSTEM_ID
,
596 CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
);
597 pci_write_config_word(0, PCI_CLASS_SUB_CODE
,
598 CONFIG_SYS_PCI_CLASSCODE_MONARCH
);
601 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
606 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
607 void pci_master_init(struct pci_controller
*hose
)
609 unsigned short temp_short
;
612 * Write the PowerPC440 EP PCI Configuration regs.
613 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
614 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
617 pci_read_config_word(0, PCI_COMMAND
, &temp_short
);
618 pci_write_config_word(0, PCI_COMMAND
,
619 temp_short
| PCI_COMMAND_MASTER
|
623 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
625 static void wait_for_pci_ready(void)
628 char *s
= getenv("pcidelay");
630 int ms
= simple_strtoul(s
, NULL
, 10);
631 printf("PCI: Waiting for %d ms\n", ms
);
636 if (!(in_be32((void*)GPIO1_IR
) & GPIO1_PPC_EREADY
)) {
637 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
643 if (in_be32((void*)GPIO1_IR
) & GPIO1_PPC_EREADY
) {
654 * This routine is called to determine if a pci scan should be
655 * performed. With various hardware environments (especially cPCI and
656 * PPMC) it's insufficient to depend on the state of the arbiter enable
657 * bit in the strap register, or generic host/adapter assumptions.
659 * Rather than hard-code a bad assumption in the general 440 code, the
660 * 440 pci code requires the board to decide at runtime.
662 * Return 0 for adapter mode, non-zero for host (monarch) mode.
664 #if defined(CONFIG_PCI)
665 int is_pci_host(struct pci_controller
*hose
)
667 char *s
= getenv("pciscan");
670 wait_for_pci_ready();
674 else if (!strcmp(s
, "yes"))
679 #endif /* defined(CONFIG_PCI) */
681 #if defined(CONFIG_POST)
683 * Returns 1 if keys pressed to start the power-on long-running tests
684 * Called from board_init_f().
686 int post_hotkeys_pressed(void)
688 return 0; /* No hotkeys supported */
690 #endif /* CONFIG_POST */
692 #ifdef CONFIG_RESET_PHY_R
695 if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR
, 0x1f, 0x0001) == 0) {
696 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR
, 0x11, 0x0010);
697 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR
, 0x11, 0x0df0);
698 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR
, 0x10, 0x0e10);
699 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR
, 0x1f, 0x0000);
702 if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR
, 0x1f, 0x0001) == 0) {
703 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR
, 0x11, 0x0010);
704 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR
, 0x11, 0x0df0);
705 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR
, 0x10, 0x0e10);
706 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR
, 0x1f, 0x0000);
711 #if defined(CONFIG_SYS_EEPROM_WREN)
713 * Input: <dev_addr> I2C address of EEPROM device to enable.
714 * <state> -1: deliver current state
717 * Returns: -1: wrong device address
718 * 0: dis-/en- able done
719 * 0/1: current state if <state> was -1.
721 int eeprom_write_enable(unsigned dev_addr
, int state
)
723 if ((CONFIG_SYS_I2C_EEPROM_ADDR
!= dev_addr
) &&
724 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR
!= dev_addr
)) {
729 /* Enable write access, clear bit GPIO_SINT2. */
730 out32(GPIO0_OR
, in32(GPIO0_OR
) & ~GPIO0_EP_EEP
);
734 /* Disable write access, set bit GPIO_SINT2. */
735 out32(GPIO0_OR
, in32(GPIO0_OR
) | GPIO0_EP_EEP
);
739 /* Read current status back. */
740 state
= (0 == (in32(GPIO0_OR
) & GPIO0_EP_EEP
));
746 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
748 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
749 int bootstrap_eeprom_write(unsigned dev_addr
, unsigned offset
,
750 uchar
*buffer
, unsigned cnt
)
752 unsigned end
= offset
+ cnt
;
756 #if defined(CONFIG_SYS_EEPROM_WREN)
757 eeprom_write_enable(dev_addr
, 1);
760 * Write data until done or would cross a write page boundary.
761 * We must write the address again when changing pages
762 * because the address counter only increments within a page.
765 while (offset
< end
) {
770 blk_off
= offset
& 0xFF; /* block offset */
772 addr
[0] = offset
>> 8; /* block number */
773 addr
[1] = blk_off
; /* block offset */
775 addr
[0] |= dev_addr
; /* insert device address */
779 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
780 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
782 maxlen
= BOOT_EEPROM_PAGE_SIZE
-
783 BOOT_EEPROM_PAGE_OFFSET(blk_off
);
784 if (maxlen
> I2C_RXTX_LEN
)
785 maxlen
= I2C_RXTX_LEN
;
790 if (i2c_write (addr
[0], offset
, alen
-1, buffer
, len
) != 0)
796 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
797 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
* 1000);
800 #if defined(CONFIG_SYS_EEPROM_WREN)
801 eeprom_write_enable(dev_addr
, 0);
806 int bootstrap_eeprom_read (unsigned dev_addr
, unsigned offset
,
807 uchar
*buffer
, unsigned cnt
)
809 unsigned end
= offset
+ cnt
;
814 * Read data until done or would cross a page boundary.
815 * We must write the address again when changing pages
816 * because the next page may be in a different device.
818 while (offset
< end
) {
823 blk_off
= offset
& 0xFF; /* block offset */
825 addr
[0] = offset
>> 8; /* block number */
826 addr
[1] = blk_off
; /* block offset */
829 addr
[0] |= dev_addr
; /* insert device address */
833 maxlen
= 0x100 - blk_off
;
834 if (maxlen
> I2C_RXTX_LEN
)
835 maxlen
= I2C_RXTX_LEN
;
839 if (i2c_read (addr
[0], offset
, alen
-1, buffer
, len
) != 0)
848 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
849 int usb_board_init(void)
851 char *act
= getenv("usbact");
854 if ((act
== NULL
|| strcmp(act
, "hostdev") == 0) &&
855 !(in_be32((void*)GPIO0_IR
) & GPIO0_USB_PRSNT
))
856 /* enable power on USB socket */
857 out_be32((void*)GPIO1_OR
,
858 in_be32((void*)GPIO1_OR
) & ~GPIO1_USB_PWR_N
);
860 for (i
=0; i
<1000; i
++)
866 int usb_board_stop(void)
868 /* disable power on USB socket */
869 out_be32((void*)GPIO1_OR
, in_be32((void*)GPIO1_OR
) | GPIO1_USB_PWR_N
);
873 int usb_board_init_fail(void)
878 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */