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[people/ms/u-boot.git] / board / esd / pmc440 / pmc440.c
1 /*
2 * (Cg) Copyright 2007-2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on board/amcc/sequoia/sequoia.c
5 *
6 * (C) Copyright 2006
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * (C) Copyright 2006
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 *
13 * SPDX-License-Identifier: GPL-2.0+
14 */
15
16 #include <common.h>
17 #include <libfdt.h>
18 #include <fdt_support.h>
19 #include <asm/ppc440.h>
20 #include <asm/processor.h>
21 #include <asm/io.h>
22 #include <asm/bitops.h>
23 #include <command.h>
24 #include <i2c.h>
25 #ifdef CONFIG_RESET_PHY_R
26 #include <miiphy.h>
27 #endif
28 #include <serial.h>
29 #include <asm/4xx_pci.h>
30
31 #include "fpga.h"
32 #include "pmc440.h"
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
37 extern void __ft_board_setup(void *blob, bd_t *bd);
38
39 ulong flash_get_size(ulong base, int banknum);
40 int pci_is_66mhz(void);
41 int is_monarch(void);
42 int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
43 uchar *buffer, unsigned cnt);
44
45 struct serial_device *default_serial_console(void)
46 {
47 uchar buf[4];
48 ulong delay;
49 int i;
50 ulong val;
51
52 /*
53 * Use default console on P4 when strapping jumper
54 * is installed (bootstrap option != 'H').
55 */
56 mfsdr(SDR0_PINSTP, val);
57 if (((val & 0xf0000000) >> 29) != 7)
58 return &eserial2_device;
59
60 ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
61 if (!(scratchreg & 0x80)) {
62 /* mark scratchreg valid */
63 scratchreg = (scratchreg & 0xffffff00) | 0x80;
64
65 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
66 0x10, buf, 4);
67 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
68 scratchreg |= buf[2];
69
70 /* bringup delay for console */
71 for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
72 udelay(1000);
73 }
74 } else
75 scratchreg |= 0x01;
76 out_be32((void*)GPIO0_ISR3L, scratchreg);
77 }
78
79 if (scratchreg & 0x01)
80 return &eserial2_device;
81 else
82 return &eserial1_device;
83 }
84
85 int board_early_init_f(void)
86 {
87 u32 sdr0_cust0;
88 u32 sdr0_pfc1, sdr0_pfc2;
89 u32 reg;
90
91 /* general EBC configuration (disable EBC timeouts) */
92 mtdcr(EBC0_CFGADDR, EBC0_CFG);
93 mtdcr(EBC0_CFGDATA, 0xf8400000);
94
95 /*
96 * Setup the GPIO pins
97 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
98 */
99 out_be32((void *)GPIO0_OR, 0x40000102);
100 out_be32((void *)GPIO0_TCR, 0x4c90011f);
101 out_be32((void *)GPIO0_OSRL, 0x28051400);
102 out_be32((void *)GPIO0_OSRH, 0x55005000);
103 out_be32((void *)GPIO0_TSRL, 0x08051400);
104 out_be32((void *)GPIO0_TSRH, 0x55005000);
105 out_be32((void *)GPIO0_ISR1L, 0x54000000);
106 out_be32((void *)GPIO0_ISR1H, 0x00000000);
107 out_be32((void *)GPIO0_ISR2L, 0x44000000);
108 out_be32((void *)GPIO0_ISR2H, 0x00000100);
109 out_be32((void *)GPIO0_ISR3L, 0x00000000);
110 out_be32((void *)GPIO0_ISR3H, 0x00000000);
111
112 out_be32((void *)GPIO1_OR, 0x80002408);
113 out_be32((void *)GPIO1_TCR, 0xd6003c08);
114 out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
115 out_be32((void *)GPIO1_OSRH, 0x00000000);
116 out_be32((void *)GPIO1_TSRL, 0x00000000);
117 out_be32((void *)GPIO1_TSRH, 0x00000000);
118 out_be32((void *)GPIO1_ISR1L, 0x00005555);
119 out_be32((void *)GPIO1_ISR1H, 0x40000000);
120 out_be32((void *)GPIO1_ISR2L, 0x04010000);
121 out_be32((void *)GPIO1_ISR2H, 0x00000000);
122 out_be32((void *)GPIO1_ISR3L, 0x01400000);
123 out_be32((void *)GPIO1_ISR3H, 0x00000000);
124
125 /* patch PLB:PCI divider for 66MHz PCI */
126 mfcpr(CPR0_SPCID, reg);
127 if (pci_is_66mhz() && (reg != 0x02000000)) {
128 mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
129
130 mfcpr(CPR0_ICFG, reg);
131 reg |= CPR0_ICFG_RLI_MASK;
132 mtcpr(CPR0_ICFG, reg);
133
134 mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
135 }
136
137 /*
138 * Setup the interrupt controller polarities, triggers, etc.
139 */
140 mtdcr(UIC0SR, 0xffffffff); /* clear all */
141 mtdcr(UIC0ER, 0x00000000); /* disable all */
142 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
143 mtdcr(UIC0PR, 0xfffff7ef);
144 mtdcr(UIC0TR, 0x00000000);
145 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
146 mtdcr(UIC0SR, 0xffffffff); /* clear all */
147
148 mtdcr(UIC1SR, 0xffffffff); /* clear all */
149 mtdcr(UIC1ER, 0x00000000); /* disable all */
150 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
151 mtdcr(UIC1PR, 0xffffc7f5);
152 mtdcr(UIC1TR, 0x00000000);
153 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
154 mtdcr(UIC1SR, 0xffffffff); /* clear all */
155
156 mtdcr(UIC2SR, 0xffffffff); /* clear all */
157 mtdcr(UIC2ER, 0x00000000); /* disable all */
158 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
159 mtdcr(UIC2PR, 0x27ffffff);
160 mtdcr(UIC2TR, 0x00000000);
161 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
162 mtdcr(UIC2SR, 0xffffffff); /* clear all */
163
164 /* select Ethernet pins */
165 mfsdr(SDR0_PFC1, sdr0_pfc1);
166 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
167 SDR0_PFC1_SELECT_CONFIG_4;
168 mfsdr(SDR0_PFC2, sdr0_pfc2);
169 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
170 SDR0_PFC2_SELECT_CONFIG_4;
171
172 /* enable 2nd IIC */
173 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
174
175 mtsdr(SDR0_PFC2, sdr0_pfc2);
176 mtsdr(SDR0_PFC1, sdr0_pfc1);
177
178 /* setup NAND FLASH */
179 mfsdr(SDR0_CUST0, sdr0_cust0);
180 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
181 SDR0_CUST0_NDFC_ENABLE |
182 SDR0_CUST0_NDFC_BW_8_BIT |
183 SDR0_CUST0_NDFC_ARE_MASK |
184 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
185 mtsdr(SDR0_CUST0, sdr0_cust0);
186
187 return 0;
188 }
189
190 #if defined(CONFIG_MISC_INIT_F)
191 int misc_init_f(void)
192 {
193 struct pci_controller hose;
194 hose.first_busno = 0;
195 hose.last_busno = 0;
196 hose.region_count = 0;
197
198 if (getenv("pciearly") && (!is_monarch())) {
199 printf("PCI: early target init\n");
200 pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
201 pci_target_init(&hose);
202 }
203 return 0;
204 }
205 #endif
206
207 /*
208 * misc_init_r.
209 */
210 int misc_init_r(void)
211 {
212 uint pbcr;
213 int size_val = 0;
214 u32 reg;
215 unsigned long usb2d0cr = 0;
216 unsigned long usb2phy0cr, usb2h0cr = 0;
217 unsigned long sdr0_pfc1;
218 unsigned long sdr0_srst0, sdr0_srst1;
219 char *act = getenv("usbact");
220
221 /*
222 * FLASH stuff...
223 */
224
225 /* Re-do sizing to get full correct info */
226
227 /* adjust flash start and offset */
228 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
229 gd->bd->bi_flashoffset = 0;
230
231 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
232 mtdcr(EBC0_CFGADDR, PB2CR);
233 #else
234 mtdcr(EBC0_CFGADDR, PB0CR);
235 #endif
236 pbcr = mfdcr(EBC0_CFGDATA);
237 size_val = ffs(gd->bd->bi_flashsize) - 21;
238 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
239 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
240 mtdcr(EBC0_CFGADDR, PB2CR);
241 #else
242 mtdcr(EBC0_CFGADDR, PB0CR);
243 #endif
244 mtdcr(EBC0_CFGDATA, pbcr);
245
246 /*
247 * Re-check to get correct base address
248 */
249 flash_get_size(gd->bd->bi_flashstart, 0);
250
251 #ifdef CONFIG_ENV_IS_IN_FLASH
252 /* Monitor protection ON by default */
253 (void)flash_protect(FLAG_PROTECT_SET,
254 -CONFIG_SYS_MONITOR_LEN,
255 0xffffffff,
256 &flash_info[0]);
257
258 /* Env protection ON by default */
259 (void)flash_protect(FLAG_PROTECT_SET,
260 CONFIG_ENV_ADDR_REDUND,
261 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
262 &flash_info[0]);
263 #endif
264
265 /*
266 * USB suff...
267 */
268 if ((act == NULL || strcmp(act, "host") == 0) &&
269 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
270 /* SDR Setting */
271 mfsdr(SDR0_PFC1, sdr0_pfc1);
272 mfsdr(SDR0_USB2D0CR, usb2d0cr);
273 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
274 mfsdr(SDR0_USB2H0CR, usb2h0cr);
275
276 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
277 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
278 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
279 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
280 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
281 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
282 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
283 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
284 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
285 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
286
287 /*
288 * An 8-bit/60MHz interface is the only possible alternative
289 * when connecting the Device to the PHY
290 */
291 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
292 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
293
294 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
295 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
296
297 mtsdr(SDR0_PFC1, sdr0_pfc1);
298 mtsdr(SDR0_USB2D0CR, usb2d0cr);
299 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
300 mtsdr(SDR0_USB2H0CR, usb2h0cr);
301
302 /*
303 * Take USB out of reset:
304 * -Initial status = all cores are in reset
305 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
306 * -wait 1 ms
307 * -deassert reset to PHY
308 * -wait 1 ms
309 * -deassert reset to HOST
310 * -wait 4 ms
311 * -deassert all other resets
312 */
313 mfsdr(SDR0_SRST1, sdr0_srst1);
314 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
315 SDR0_SRST1_P4OPB0 | \
316 SDR0_SRST1_OPBA2 | \
317 SDR0_SRST1_PLB42OPB1 | \
318 SDR0_SRST1_OPB2PLB40);
319 mtsdr(SDR0_SRST1, sdr0_srst1);
320 udelay(1000);
321
322 mfsdr(SDR0_SRST1, sdr0_srst1);
323 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
324 mtsdr(SDR0_SRST1, sdr0_srst1);
325 udelay(1000);
326
327 mfsdr(SDR0_SRST0, sdr0_srst0);
328 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
329 mtsdr(SDR0_SRST0, sdr0_srst0);
330 udelay(4000);
331
332 /* finally all the other resets */
333 mtsdr(SDR0_SRST1, 0x00000000);
334 mtsdr(SDR0_SRST0, 0x00000000);
335
336 if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
337 /* enable power on USB socket */
338 out_be32((void*)GPIO1_OR,
339 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
340 }
341
342 printf("USB: Host\n");
343
344 } else if ((strcmp(act, "dev") == 0) ||
345 (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
346 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
347
348 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
349 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
350 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
351 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
352 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
353 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
354 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
355 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
356 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
357
358 udelay (1000);
359 mtsdr(SDR0_SRST1, 0x672c6000);
360
361 udelay (1000);
362 mtsdr(SDR0_SRST0, 0x00000080);
363
364 udelay (1000);
365 mtsdr(SDR0_SRST1, 0x60206000);
366
367 *(unsigned int *)(0xe0000350) = 0x00000001;
368
369 udelay (1000);
370 mtsdr(SDR0_SRST1, 0x60306000);
371
372 /* SDR Setting */
373 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
374 mfsdr(SDR0_USB2H0CR, usb2h0cr);
375 mfsdr(SDR0_USB2D0CR, usb2d0cr);
376 mfsdr(SDR0_PFC1, sdr0_pfc1);
377
378 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
379 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
380 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
381 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
382 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
383 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
384 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
385 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
386 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
387 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
388
389 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
390 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
391
392 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
393
394 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
395 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
396
397 mtsdr(SDR0_USB2H0CR, usb2h0cr);
398 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
399 mtsdr(SDR0_USB2D0CR, usb2d0cr);
400 mtsdr(SDR0_PFC1, sdr0_pfc1);
401
402 /*clear resets*/
403 udelay(1000);
404 mtsdr(SDR0_SRST1, 0x00000000);
405 udelay(1000);
406 mtsdr(SDR0_SRST0, 0x00000000);
407
408 printf("USB: Device\n");
409 }
410
411 /*
412 * Clear PLB4A0_ACR[WRP]
413 * This fix will make the MAL burst disabling patch for the Linux
414 * EMAC driver obsolete.
415 */
416 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
417 mtdcr(PLB4A0_ACR, reg);
418
419 #ifdef CONFIG_FPGA
420 pmc440_init_fpga();
421 #endif
422
423 /* turn off POST LED */
424 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
425 /* turn on RUN LED */
426 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
427 return 0;
428 }
429
430 int is_monarch(void)
431 {
432 if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
433 return 0;
434
435 return 1;
436 }
437
438 int pci_is_66mhz(void)
439 {
440 if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
441 return 1;
442 return 0;
443 }
444
445 int board_revision(void)
446 {
447 return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
448 }
449
450 int checkboard(void)
451 {
452 puts("Board: esd GmbH - PMC440");
453
454 gd->board_type = board_revision();
455 printf(", Rev 1.%ld, ", gd->board_type);
456
457 if (!is_monarch()) {
458 puts("non-");
459 }
460
461 printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
462 return (0);
463 }
464
465
466 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
467 /*
468 * Assign interrupts to PCI devices. Some OSs rely on this.
469 */
470 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
471 {
472 unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
473
474 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
475 int_line[PCI_DEV(dev) & 0x03]);
476 }
477 #endif
478
479 /*
480 * pci_target_init
481 *
482 * The bootstrap configuration provides default settings for the pci
483 * inbound map (PIM). But the bootstrap config choices are limited and
484 * may not be sufficient for a given board.
485 */
486 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
487 void pci_target_init(struct pci_controller *hose)
488 {
489 char *ptmla_str, *ptmms_str;
490
491 /*
492 * Set up Direct MMIO registers
493 */
494 /*
495 * PowerPC440EPX PCI Master configuration.
496 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
497 * PLB address 0x80000000-0xBFFFFFFF
498 * ==> PCI address 0x80000000-0xBFFFFFFF
499 * Use byte reversed out routines to handle endianess.
500 * Make this region non-prefetchable.
501 */
502 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
503 /* - disabled b4 setting */
504 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
505 out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
506 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
507 out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
508 /* and enable region */
509
510 if (!is_monarch()) {
511 ptmla_str = getenv("ptm1la");
512 ptmms_str = getenv("ptm1ms");
513 if(NULL != ptmla_str && NULL != ptmms_str ) {
514 out32r(PCIL0_PTM1MS,
515 simple_strtoul(ptmms_str, NULL, 16));
516 out32r(PCIL0_PTM1LA,
517 simple_strtoul(ptmla_str, NULL, 16));
518 } else {
519 /* BAR1: default top 64MB of RAM */
520 out32r(PCIL0_PTM1MS, 0xfc000001);
521 out32r(PCIL0_PTM1LA, 0x0c000000);
522 }
523 } else {
524 /* BAR1: default: complete 256MB RAM */
525 out32r(PCIL0_PTM1MS, 0xf0000001);
526 out32r(PCIL0_PTM1LA, 0x00000000);
527 }
528
529 ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
530 ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
531 if(NULL != ptmla_str && NULL != ptmms_str ) {
532 out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
533 out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
534 } else {
535 /* BAR2: default: 4MB FPGA */
536 out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
537 out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
538 }
539
540 if (is_monarch()) {
541 /* BAR2: map FPGA registers behind system memory at 1GB */
542 pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
543 }
544
545 /*
546 * Set up Configuration registers
547 */
548
549 /* Program the board's vendor id */
550 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
551 CONFIG_SYS_PCI_SUBSYS_VENDORID);
552
553 /* disabled for PMC405 backward compatibility */
554 /* Configure command register as bus master */
555 /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
556
557
558 /* 240nS PCI clock */
559 pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
560
561 /* No error reporting */
562 pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
563
564 if (!is_monarch()) {
565 /* Program the board's subsystem id/classcode */
566 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
567 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
568 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
569 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
570
571 /* PCI configuration done: release ERREADY */
572 out_be32((void*)GPIO1_OR,
573 in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
574 out_be32((void*)GPIO1_TCR,
575 in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
576 } else {
577 /* Program the board's subsystem id/classcode */
578 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
579 CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
580 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
581 CONFIG_SYS_PCI_CLASSCODE_MONARCH);
582 }
583
584 /* enable host configuration */
585 pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
586 }
587 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
588
589 /*
590 * Override weak default pci_master_init()
591 */
592 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
593 void pci_master_init(struct pci_controller *hose)
594 {
595 /*
596 * Only configure the master in monach mode
597 */
598 if (is_monarch())
599 __pci_master_init(hose);
600 }
601 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
602
603 static void wait_for_pci_ready(void)
604 {
605 if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
606 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
607 while (1) {
608 if (ctrlc()) {
609 puts("abort\n");
610 break;
611 }
612 if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
613 printf("done\n");
614 break;
615 }
616 }
617 }
618 }
619
620 /*
621 * Override weak is_pci_host()
622 *
623 * This routine is called to determine if a pci scan should be
624 * performed. With various hardware environments (especially cPCI and
625 * PPMC) it's insufficient to depend on the state of the arbiter enable
626 * bit in the strap register, or generic host/adapter assumptions.
627 *
628 * Rather than hard-code a bad assumption in the general 440 code, the
629 * 440 pci code requires the board to decide at runtime.
630 *
631 * Return 0 for adapter mode, non-zero for host (monarch) mode.
632 */
633 #if defined(CONFIG_PCI)
634 int is_pci_host(struct pci_controller *hose)
635 {
636 char *s = getenv("pciscan");
637 if (s == NULL)
638 if (is_monarch()) {
639 wait_for_pci_ready();
640 return 1;
641 } else
642 return 0;
643 else if (!strcmp(s, "yes"))
644 return 1;
645
646 return 0;
647 }
648 #endif /* defined(CONFIG_PCI) */
649
650 #ifdef CONFIG_RESET_PHY_R
651 void reset_phy(void)
652 {
653 char *s;
654 unsigned short val_method, val_behavior;
655
656 /* special LED setup for NGCC/CANDES */
657 if ((s = getenv("bd_type")) &&
658 ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
659 val_method = 0x0e0a;
660 val_behavior = 0x0cf2;
661 } else {
662 /* PMC440 standard type */
663 val_method = 0x0e10;
664 val_behavior = 0x0cf0;
665 }
666
667 if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
668 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
669 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
670 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
671 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
672 }
673
674 if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
675 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
676 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
677 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
678 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
679 }
680 }
681 #endif
682
683 #if defined(CONFIG_SYS_EEPROM_WREN)
684 /*
685 * Input: <dev_addr> I2C address of EEPROM device to enable.
686 * <state> -1: deliver current state
687 * 0: disable write
688 * 1: enable write
689 * Returns: -1: wrong device address
690 * 0: dis-/en- able done
691 * 0/1: current state if <state> was -1.
692 */
693 int eeprom_write_enable(unsigned dev_addr, int state)
694 {
695 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
696 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
697 return -1;
698 } else {
699 switch (state) {
700 case 1:
701 /* Enable write access, clear bit GPIO_SINT2. */
702 out_be32((void *)GPIO0_OR,
703 in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
704 state = 0;
705 break;
706 case 0:
707 /* Disable write access, set bit GPIO_SINT2. */
708 out_be32((void *)GPIO0_OR,
709 in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
710 state = 0;
711 break;
712 default:
713 /* Read current status back. */
714 state = (0 == (in_be32((void *)GPIO0_OR)
715 & GPIO0_EP_EEP));
716 break;
717 }
718 }
719 return state;
720 }
721 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
722
723 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
724 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
725 uchar *buffer, unsigned cnt)
726 {
727 unsigned end = offset + cnt;
728 unsigned blk_off;
729 int rcode = 0;
730
731 #if defined(CONFIG_SYS_EEPROM_WREN)
732 eeprom_write_enable(dev_addr, 1);
733 #endif
734 /*
735 * Write data until done or would cross a write page boundary.
736 * We must write the address again when changing pages
737 * because the address counter only increments within a page.
738 */
739
740 while (offset < end) {
741 unsigned alen, len;
742 unsigned maxlen;
743 uchar addr[2];
744
745 blk_off = offset & 0xFF; /* block offset */
746
747 addr[0] = offset >> 8; /* block number */
748 addr[1] = blk_off; /* block offset */
749 alen = 2;
750 addr[0] |= dev_addr; /* insert device address */
751
752 len = end - offset;
753
754 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
755 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
756
757 maxlen = BOOT_EEPROM_PAGE_SIZE -
758 BOOT_EEPROM_PAGE_OFFSET(blk_off);
759 if (maxlen > I2C_RXTX_LEN)
760 maxlen = I2C_RXTX_LEN;
761
762 if (len > maxlen)
763 len = maxlen;
764
765 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
766 rcode = 1;
767
768 buffer += len;
769 offset += len;
770
771 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
772 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
773 #endif
774 }
775 #if defined(CONFIG_SYS_EEPROM_WREN)
776 eeprom_write_enable(dev_addr, 0);
777 #endif
778 return rcode;
779 }
780
781 int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
782 uchar *buffer, unsigned cnt)
783 {
784 unsigned end = offset + cnt;
785 unsigned blk_off;
786 int rcode = 0;
787
788 /*
789 * Read data until done or would cross a page boundary.
790 * We must write the address again when changing pages
791 * because the next page may be in a different device.
792 */
793 while (offset < end) {
794 unsigned alen, len;
795 unsigned maxlen;
796 uchar addr[2];
797
798 blk_off = offset & 0xFF; /* block offset */
799
800 addr[0] = offset >> 8; /* block number */
801 addr[1] = blk_off; /* block offset */
802 alen = 2;
803
804 addr[0] |= dev_addr; /* insert device address */
805
806 len = end - offset;
807
808 maxlen = 0x100 - blk_off;
809 if (maxlen > I2C_RXTX_LEN)
810 maxlen = I2C_RXTX_LEN;
811 if (len > maxlen)
812 len = maxlen;
813
814 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
815 rcode = 1;
816 buffer += len;
817 offset += len;
818 }
819
820 return rcode;
821 }
822
823 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
824 int usb_board_init(void)
825 {
826 char *act = getenv("usbact");
827 int i;
828
829 if ((act == NULL || strcmp(act, "host") == 0) &&
830 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
831 /* enable power on USB socket */
832 out_be32((void*)GPIO1_OR,
833 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
834
835 for (i=0; i<1000; i++)
836 udelay(1000);
837
838 return 0;
839 }
840
841 int usb_board_stop(void)
842 {
843 /* disable power on USB socket */
844 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
845 return 0;
846 }
847
848 int usb_board_init_fail(void)
849 {
850 usb_board_stop();
851 return 0;
852 }
853 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
854
855 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
856 void ft_board_setup(void *blob, bd_t *bd)
857 {
858 int rc;
859
860 __ft_board_setup(blob, bd);
861
862 /*
863 * Disable PCI in non-monarch mode.
864 */
865 if (!is_monarch()) {
866 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
867 "disabled", sizeof("disabled"), 1);
868 if (rc) {
869 printf("Unable to update property status in PCI node, err=%s\n",
870 fdt_strerror(rc));
871 }
872 }
873 }
874 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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