board/evb64260/intel_flash.h

   1 /*************** DEFINES for Intel StrataFlash FLASH chip ********************/
   2
   3 /*
   4  * acceptable chips types are:
   5  *
   6  *      28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
   7  */
   8
   9 /* register addresses, valid only following an CHIP_CMD_RD_ID command */
  10 #define CHIP_ADDR_REG_MAN       0x000000        /* manufacturer's id */
  11 #define CHIP_ADDR_REG_DEV       0x000001        /* device id */
  12 #define CHIP_ADDR_REG_CFGM      0x000003        /* master lock config */
  13 #define CHIP_ADDR_REG_CFG(b)    (((b)<<16)|2)   /* lock config for block b */
  14
  15 /* Commands */
  16 #define CHIP_CMD_RST            0xFF            /* reset flash */
  17 #define CHIP_CMD_RD_ID          0x90            /* read the id and lock bits */
  18 #define CHIP_CMD_RD_QUERY       0x98            /* read device capabilities */
  19 #define CHIP_CMD_RD_STAT        0x70            /* read the status register */
  20 #define CHIP_CMD_CLR_STAT       0x50            /* clear the staus register */
  21 #define CHIP_CMD_WR_BUF         0xE8            /* clear the staus register */
  22 #define CHIP_CMD_PROG           0x40            /* program word command */
  23 #define CHIP_CMD_ERASE1         0x20            /* 1st word for block erase */
  24 #define CHIP_CMD_ERASE2         0xD0            /* 2nd word for block erase */
  25 #define CHIP_CMD_ERASE_SUSP     0xB0            /* suspend block erase */
  26 #define CHIP_CMD_LOCK           0x60            /* 1st word for all lock cmds */
  27 #define CHIP_CMD_SET_LOCK_BLK   0x01            /* 2nd wrd set block lock bit */
  28 #define CHIP_CMD_SET_LOCK_MSTR  0xF1            /* 2nd wrd set master lck bit */
  29 #define CHIP_CMD_CLR_LOCK_BLK   0xD0            /* 2nd wrd clear blk lck bit */
  30
  31 /* status register bits */
  32 #define CHIP_STAT_DPS           0x02            /* Device Protect Status */
  33 #define CHIP_STAT_VPPS          0x08            /* VPP Status */
  34 #define CHIP_STAT_PSLBS         0x10            /* Program+Set Lock Bit Stat */
  35 #define CHIP_STAT_ECLBS         0x20            /* Erase+Clr Lock Bit Stat */
  36 #define CHIP_STAT_ESS           0x40            /* Erase Suspend Status */
  37 #define CHIP_STAT_RDY           0x80            /* WSM Mach Status, 1=rdy */
  38
  39 #define CHIP_STAT_ERR           (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
  40                                     CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
  41
  42 /* ID and Lock Configuration */
  43 #define CHIP_RD_ID_LOCK         0x01            /* Bit 0 of each byte */
  44 #define CHIP_RD_ID_MAN          0x89            /* Manufacturer code = 0x89 */
  45 #define CHIP_RD_ID_DEV          CONFIG_SYS_FLASH_ID
  46
  47 /* dimensions */
  48 #define CHIP_WIDTH              2               /* chips are in 16 bit mode */
  49 #define CHIP_WSHIFT             1               /* (log2 of CHIP_WIDTH) */
  50 #define CHIP_NBLOCKS            128
  51 #define CHIP_BLKSZ              (128 * 1024)    /* of 128Kbytes each */
  52 #define CHIP_SIZE               (CHIP_BLKSZ * CHIP_NBLOCKS)
  53
  54 /********************** DEFINES for Hymod Flash ******************************/
  55
  56 /*
  57  * The hymod board has 2 x 28F320J5 chips running in
  58  * 16 bit mode, for a 32 bit wide bank.
  59  */
  60
  61 typedef unsigned short bank_word_t;             /* 8/16/32/64bit unsigned int */
  62 typedef volatile bank_word_t *bank_addr_t;
  63 typedef unsigned long bank_size_t;              /* want this big - >= 32 bit */
  64
  65 #define BANK_CHIP_WIDTH         1               /* each bank is 1 chip wide */
  66 #define BANK_CHIP_WSHIFT        0               /* (log2 of BANK_CHIP_WIDTH) */
  67
  68 #define BANK_WIDTH              (CHIP_WIDTH * BANK_CHIP_WIDTH)
  69 #define BANK_WSHIFT             (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
  70 #define BANK_NBLOCKS            CHIP_NBLOCKS
  71 #define BANK_BLKSZ              (CHIP_BLKSZ * BANK_CHIP_WIDTH)
  72 #define BANK_SIZE               (CHIP_SIZE * BANK_CHIP_WIDTH)
  73
  74 #define MAX_BANKS               1               /* only one bank possible */
  75
  76 /* align bank addresses and sizes to bank word boundaries */
  77 #define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
  78                                     & ~(BANK_WIDTH - 1)))
  79 #define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
  80                                     (bank_size_t)(s) + (BANK_WIDTH - 1)))
  81
  82 /* align bank addresses and sizes to bank block boundaries */
  83 #define BANK_ADDR_BLK_ALIGN(a)  ((bank_addr_t)((bank_size_t)(a) \
  84                                     & ~(BANK_BLKSZ - 1)))
  85 #define BANK_SIZE_BLK_ALIGN(s)  ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
  86                                     (bank_size_t)(s) + (BANK_BLKSZ - 1)))
  87
  88 /* align bank addresses and sizes to bank boundaries */
  89 #define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
  90                                     & ~(BANK_SIZE - 1)))
  91 #define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
  92                                     (bank_size_t)(s) + (BANK_SIZE - 1)))
  93
  94 /* add an offset to a bank address */
  95 #define BANK_ADDR_OFFSET(a, o)  (bank_addr_t)((bank_size_t)(a) + \
  96                                     (bank_size_t)(o))
  97
  98 /* get base address of bank b, given flash base address a */
  99 #define BANK_ADDR_BASE(a, b)    BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
 100                                     (bank_size_t)(b) * BANK_SIZE)
 101
 102 /* adjust a bank address to start of next word, block or bank */
 103 #define BANK_ADDR_NEXT_WORD(a)  BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
 104                                     BANK_WIDTH)
 105 #define BANK_ADDR_NEXT_BLK(a)   BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
 106                                     BANK_BLKSZ)
 107 #define BANK_ADDR_NEXT_BANK(a)  BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
 108                                     BANK_SIZE)
 109
 110 /* get bank address of chip register r given a bank base address a */
 111 #define BANK_ADDR_REG(a, r)     BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
 112                                     ((bank_size_t)(r) << BANK_WSHIFT))
 113
 114 /* make a bank address for each chip register address */
 115
 116 #define BANK_ADDR_REG_MAN(a)    BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
 117 #define BANK_ADDR_REG_DEV(a)    BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
 118 #define BANK_ADDR_REG_CFGM(a)   BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
 119 #define BANK_ADDR_REG_CFG(b,a)  BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
 120
 121 /*
 122  * replicate a chip cmd/stat/rd value into each byte position within a word
 123  * so that multiple chips are accessed in a single word i/o operation
 124  *
 125  * this must be as wide as the bank_word_t type, and take into account the
 126  * chip width and bank layout
 127  */
 128
 129 #define BANK_FILL_WORD(o)       ((bank_word_t)(o))
 130
 131 /* make a bank word value for each chip cmd/stat/rd value */
 132
 133 /* Commands */
 134 #define BANK_CMD_RST            BANK_FILL_WORD(CHIP_CMD_RST)
 135 #define BANK_CMD_RD_ID          BANK_FILL_WORD(CHIP_CMD_RD_ID)
 136 #define BANK_CMD_RD_STAT        BANK_FILL_WORD(CHIP_CMD_RD_STAT)
 137 #define BANK_CMD_CLR_STAT       BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
 138 #define BANK_CMD_ERASE1         BANK_FILL_WORD(CHIP_CMD_ERASE1)
 139 #define BANK_CMD_ERASE2         BANK_FILL_WORD(CHIP_CMD_ERASE2)
 140 #define BANK_CMD_PROG           BANK_FILL_WORD(CHIP_CMD_PROG)
 141 #define BANK_CMD_LOCK           BANK_FILL_WORD(CHIP_CMD_LOCK)
 142 #define BANK_CMD_SET_LOCK_BLK   BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
 143 #define BANK_CMD_SET_LOCK_MSTR  BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
 144 #define BANK_CMD_CLR_LOCK_BLK   BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
 145
 146 /* status register bits */
 147 #define BANK_STAT_DPS           BANK_FILL_WORD(CHIP_STAT_DPS)
 148 #define BANK_STAT_PSS           BANK_FILL_WORD(CHIP_STAT_PSS)
 149 #define BANK_STAT_VPPS          BANK_FILL_WORD(CHIP_STAT_VPPS)
 150 #define BANK_STAT_PSLBS         BANK_FILL_WORD(CHIP_STAT_PSLBS)
 151 #define BANK_STAT_ECLBS         BANK_FILL_WORD(CHIP_STAT_ECLBS)
 152 #define BANK_STAT_ESS           BANK_FILL_WORD(CHIP_STAT_ESS)
 153 #define BANK_STAT_RDY           BANK_FILL_WORD(CHIP_STAT_RDY)
 154
 155 #define BANK_STAT_ERR           BANK_FILL_WORD(CHIP_STAT_ERR)
 156
 157 /* ID and Lock Configuration */
 158 #define BANK_RD_ID_LOCK         BANK_FILL_WORD(CHIP_RD_ID_LOCK)
 159 #define BANK_RD_ID_MAN          BANK_FILL_WORD(CHIP_RD_ID_MAN)
 160 #define BANK_RD_ID_DEV          BANK_FILL_WORD(CHIP_RD_ID_DEV)