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[people/ms/u-boot.git] / board / evb64260 / pci.c
1 /* PCI.c - PCI functions */
2
3 /* Copyright - Galileo technology. */
4
5 #include <common.h>
6 #include <pci.h>
7
8 #include <galileo/pci.h>
9
10 static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
11 #ifdef CONFIG_ZUMA_V2
12 {0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0},
13 {0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0}
14 #else /* EVB??? This is a guess */
15 {0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0},
16 {0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0}
17 #endif
18 };
19
20 static const unsigned int pci_p2p_configuration_reg[] = {
21 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
22 };
23
24 static const unsigned int pci_configuration_address[] = {
25 PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
26 };
27
28 static const unsigned int pci_configuration_data[] = {
29 PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
30 PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
31 };
32
33 static const unsigned int pci_error_cause_reg[] = {
34 PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
35 };
36
37 static const unsigned int pci_arbiter_control[] = {
38 PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
39 };
40
41 static const unsigned int pci_snoop_control_base_0_low[] = {
42 PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
43 };
44 static const unsigned int pci_snoop_control_top_0[] = {
45 PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
46 };
47
48 static const unsigned int pci_access_control_base_0_low[] = {
49 PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
50 };
51 static const unsigned int pci_access_control_top_0[] = {
52 PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
53 };
54
55 static const unsigned int pci_scs_bank_size[2][4] = {
56 {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
57 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
58 {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
59 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
60 };
61
62 static const unsigned int pci_p2p_configuration[] = {
63 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
64 };
65
66 static unsigned int local_buses[] = { 0, 0 };
67
68 /********************************************************************
69 * pciWriteConfigReg - Write to a PCI configuration register
70 * - Make sure the GT is configured as a master before writing
71 * to another device on the PCI.
72 * - The function takes care of Big/Little endian conversion.
73 *
74 *
75 * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
76 * (or any other PCI device spec)
77 * pciDevNum: The device number needs to be addressed.
78 *
79 * Configuration Address 0xCF8:
80 *
81 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
82 * |congif|Reserved| Bus |Device|Function|Register|00|
83 * |Enable| |Number|Number| Number | Number | | <=field Name
84 *
85 *********************************************************************/
86 void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
87 unsigned int pciDevNum, unsigned int data)
88 {
89 volatile unsigned int DataForAddrReg;
90 unsigned int functionNum;
91 unsigned int busNum = PCI_BUS (pciDevNum);
92 unsigned int addr;
93
94 if (pciDevNum > 32) /* illegal device Number */
95 return;
96 if (pciDevNum == SELF) { /* configure our configuration space. */
97 pciDevNum =
98 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
99 0x1f;
100 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
101 0xff0000;
102 }
103 functionNum = regOffset & 0x00000700;
104 pciDevNum = pciDevNum << 11;
105 regOffset = regOffset & 0xfc;
106 DataForAddrReg =
107 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
108 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
109 GT_REG_READ (pci_configuration_address[host], &addr);
110 if (addr != DataForAddrReg)
111 return;
112 GT_REG_WRITE (pci_configuration_data[host], data);
113 }
114
115 /********************************************************************
116 * pciReadConfigReg - Read from a PCI0 configuration register
117 * - Make sure the GT is configured as a master before reading
118 * from another device on the PCI.
119 * - The function takes care of Big/Little endian conversion.
120 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
121 * spec)
122 * pciDevNum: The device number needs to be addressed.
123 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
124 * cause register to make sure the data is valid
125 *
126 * Configuration Address 0xCF8:
127 *
128 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
129 * |congif|Reserved| Bus |Device|Function|Register|00|
130 * |Enable| |Number|Number| Number | Number | | <=field Name
131 *
132 *********************************************************************/
133 unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
134 unsigned int pciDevNum)
135 {
136 volatile unsigned int DataForAddrReg;
137 unsigned int data;
138 unsigned int functionNum;
139 unsigned int busNum = PCI_BUS (pciDevNum);
140
141 if (pciDevNum > 32) /* illegal device Number */
142 return 0xffffffff;
143 if (pciDevNum == SELF) { /* configure our configuration space. */
144 pciDevNum =
145 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
146 0x1f;
147 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
148 0xff0000;
149 }
150 functionNum = regOffset & 0x00000700;
151 pciDevNum = pciDevNum << 11;
152 regOffset = regOffset & 0xfc;
153 DataForAddrReg =
154 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
155 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
156 GT_REG_READ (pci_configuration_address[host], &data);
157 if (data != DataForAddrReg)
158 return 0xffffffff;
159 GT_REG_READ (pci_configuration_data[host], &data);
160 return data;
161 }
162
163 /********************************************************************
164 * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
165 * the agent is placed on another Bus. For more
166 * information read P2P in the PCI spec.
167 *
168 * Inputs: unsigned int regOffset - The register offset as it apears in the
169 * GT spec (or any other PCI device spec).
170 * unsigned int pciDevNum - The device number needs to be addressed.
171 * unsigned int busNum - On which bus does the Target agent connect
172 * to.
173 * unsigned int data - data to be written.
174 *
175 * Configuration Address 0xCF8:
176 *
177 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
178 * |congif|Reserved| Bus |Device|Function|Register|01|
179 * |Enable| |Number|Number| Number | Number | | <=field Name
180 *
181 * The configuration Address is configure as type-I (bits[1:0] = '01') due to
182 * PCI spec referring to P2P.
183 *
184 *********************************************************************/
185 void pciOverBridgeWriteConfigReg (PCI_HOST host,
186 unsigned int regOffset,
187 unsigned int pciDevNum,
188 unsigned int busNum, unsigned int data)
189 {
190 unsigned int DataForReg;
191 unsigned int functionNum;
192
193 functionNum = regOffset & 0x00000700;
194 pciDevNum = pciDevNum << 11;
195 regOffset = regOffset & 0xff;
196 busNum = busNum << 16;
197 if (pciDevNum == SELF) { /* This board */
198 DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
199 } else {
200 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
201 BIT31 | BIT0;
202 }
203 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
204 if (pciDevNum == SELF) { /* This board */
205 GT_REG_WRITE (pci_configuration_data[host], data);
206 } else { /* configuration Transaction over the pci. */
207
208 /* The PCI is working in LE Mode So it swap the Data. */
209 GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data));
210 }
211 }
212
213
214 /********************************************************************
215 * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
216 * the agent target locate on another PCI bus.
217 * - Make sure the GT is configured as a master
218 * before reading from another device on the PCI.
219 * - The function takes care of Big/Little endian
220 * conversion.
221 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
222 * spec). (configuration register offset.)
223 * pciDevNum: The device number needs to be addressed.
224 * busNum: the Bus number where the agent is place.
225 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
226 * cause register to make sure the data is valid
227 *
228 * Configuration Address 0xCF8:
229 *
230 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
231 * |congif|Reserved| Bus |Device|Function|Register|01|
232 * |Enable| |Number|Number| Number | Number | | <=field Name
233 *
234 *********************************************************************/
235 unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
236 unsigned int regOffset,
237 unsigned int pciDevNum,
238 unsigned int busNum)
239 {
240 unsigned int DataForReg;
241 unsigned int data;
242 unsigned int functionNum;
243
244 functionNum = regOffset & 0x00000700;
245 pciDevNum = pciDevNum << 11;
246 regOffset = regOffset & 0xff;
247 busNum = busNum << 16;
248 if (pciDevNum == SELF) { /* This board */
249 DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
250 } else { /* agent on another bus */
251
252 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
253 BIT0 | BIT31;
254 }
255 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
256 if (pciDevNum == SELF) { /* This board */
257 GT_REG_READ (pci_configuration_data[host], &data);
258 return data;
259 } else { /* The PCI is working in LE Mode So it swap the Data. */
260
261 GT_REG_READ (pci_configuration_data[host], &data);
262 return WORD_SWAP (data);
263 }
264 }
265
266 /********************************************************************
267 * pciGetRegOffset - Gets the register offset for this region config.
268 *
269 * INPUT: Bus, Region - The bus and region we ask for its base address.
270 * OUTPUT: N/A
271 * RETURNS: PCI register base address
272 *********************************************************************/
273 static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
274 {
275 switch (host) {
276 case PCI_HOST0:
277 switch (region) {
278 case PCI_IO:
279 return PCI_0I_O_LOW_DECODE_ADDRESS;
280 case PCI_REGION0:
281 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
282 case PCI_REGION1:
283 return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
284 case PCI_REGION2:
285 return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
286 case PCI_REGION3:
287 return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
288 }
289 case PCI_HOST1:
290 switch (region) {
291 case PCI_IO:
292 return PCI_1I_O_LOW_DECODE_ADDRESS;
293 case PCI_REGION0:
294 return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
295 case PCI_REGION1:
296 return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
297 case PCI_REGION2:
298 return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
299 case PCI_REGION3:
300 return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
301 }
302 }
303 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
304 }
305
306 static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
307 {
308 switch (host) {
309 case PCI_HOST0:
310 switch (region) {
311 case PCI_IO:
312 return PCI_0I_O_ADDRESS_REMAP;
313 case PCI_REGION0:
314 return PCI_0MEMORY0_ADDRESS_REMAP;
315 case PCI_REGION1:
316 return PCI_0MEMORY1_ADDRESS_REMAP;
317 case PCI_REGION2:
318 return PCI_0MEMORY2_ADDRESS_REMAP;
319 case PCI_REGION3:
320 return PCI_0MEMORY3_ADDRESS_REMAP;
321 }
322 case PCI_HOST1:
323 switch (region) {
324 case PCI_IO:
325 return PCI_1I_O_ADDRESS_REMAP;
326 case PCI_REGION0:
327 return PCI_1MEMORY0_ADDRESS_REMAP;
328 case PCI_REGION1:
329 return PCI_1MEMORY1_ADDRESS_REMAP;
330 case PCI_REGION2:
331 return PCI_1MEMORY2_ADDRESS_REMAP;
332 case PCI_REGION3:
333 return PCI_1MEMORY3_ADDRESS_REMAP;
334 }
335 }
336 return PCI_0MEMORY0_ADDRESS_REMAP;
337 }
338
339 bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
340 unsigned int bankBase, unsigned int bankLength)
341 {
342 unsigned int low = 0xfff;
343 unsigned int high = 0x0;
344 unsigned int regOffset = pciGetRegOffset (host, region);
345 unsigned int remapOffset = pciGetRemapOffset (host, region);
346
347 if (bankLength != 0) {
348 low = (bankBase >> 20) & 0xfff;
349 high = ((bankBase + bankLength) >> 20) - 1;
350 }
351
352 GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
353 GT_REG_WRITE (regOffset + 8, high);
354
355 if (bankLength != 0) { /* must do AFTER writing maps */
356 GT_REG_WRITE (remapOffset, remapBase >> 20); /* sorry, 32 bits only.
357 dont support upper 32
358 in this driver */
359 }
360 return true;
361 }
362
363 unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
364 {
365 unsigned int low;
366 unsigned int regOffset = pciGetRegOffset (host, region);
367
368 GT_REG_READ (regOffset, &low);
369 return (low & 0xfff) << 20;
370 }
371
372 unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
373 {
374 unsigned int low, high;
375 unsigned int regOffset = pciGetRegOffset (host, region);
376
377 GT_REG_READ (regOffset, &low);
378 GT_REG_READ (regOffset + 8, &high);
379 high &= 0xfff;
380 low &= 0xfff;
381 if (high <= low)
382 return 0;
383 return (high + 1 - low) << 20;
384 }
385
386 /********************************************************************
387 * pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
388 *
389 * Inputs: base and size of PCI SCS
390 *********************************************************************/
391 void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
392 unsigned int pciDramBase, unsigned int pciDramSize)
393 {
394 pciDramBase = pciDramBase & 0xfffff000;
395 pciDramBase = pciDramBase | (pciReadConfigReg (host,
396 PCI_SCS_0_BASE_ADDRESS
397 + 4 * bank,
398 SELF) & 0x00000fff);
399 pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF,
400 pciDramBase);
401 if (pciDramSize == 0)
402 pciDramSize++;
403 GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
404 }
405
406
407 /********************************************************************
408 * pciSetRegionFeatures - This function modifys one of the 8 regions with
409 * feature bits given as an input.
410 * - Be advised to check the spec before modifying them.
411 * Inputs: PCI_PROTECT_REGION region - one of the eight regions.
412 * unsigned int features - See file: pci.h there are defintion for those
413 * region features.
414 * unsigned int baseAddress - The region base Address.
415 * unsigned int topAddress - The region top Address.
416 * Returns: false if one of the parameters is erroneous true otherwise.
417 *********************************************************************/
418 bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
419 unsigned int features, unsigned int baseAddress,
420 unsigned int regionLength)
421 {
422 unsigned int accessLow;
423 unsigned int accessHigh;
424 unsigned int accessTop = baseAddress + regionLength;
425
426 if (regionLength == 0) { /* close the region. */
427 pciDisableAccessRegion (host, region);
428 return true;
429 }
430 /* base Address is store is bits [11:0] */
431 accessLow = (baseAddress & 0xfff00000) >> 20;
432 /* All the features are update according to the defines in pci.h (to be on
433 the safe side we disable bits: [11:0] */
434 accessLow = accessLow | (features & 0xfffff000);
435 /* write to the Low Access Region register */
436 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
437 accessLow);
438
439 accessHigh = (accessTop & 0xfff00000) >> 20;
440
441 /* write to the High Access Region register */
442 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
443 accessHigh - 1);
444 return true;
445 }
446
447 /********************************************************************
448 * pciDisableAccessRegion - Disable The given Region by writing MAX size
449 * to its low Address and MIN size to its high Address.
450 *
451 * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
452 * Returns: N/A.
453 *********************************************************************/
454 void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
455 {
456 /* writing back the registers default values. */
457 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
458 0x01001fff);
459 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
460 }
461
462 /********************************************************************
463 * pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
464 *
465 * Inputs: N/A
466 * Returns: true.
467 *********************************************************************/
468 bool pciArbiterEnable (PCI_HOST host)
469 {
470 unsigned int regData;
471
472 GT_REG_READ (pci_arbiter_control[host], &regData);
473 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
474 return true;
475 }
476
477 /********************************************************************
478 * pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
479 *
480 * Inputs: N/A
481 * Returns: true
482 *********************************************************************/
483 bool pciArbiterDisable (PCI_HOST host)
484 {
485 unsigned int regData;
486
487 GT_REG_READ (pci_arbiter_control[host], &regData);
488 GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
489 return true;
490 }
491
492 /********************************************************************
493 * pciParkingDisable - Park on last option disable, with this function you can
494 * disable the park on last mechanism for each agent.
495 * disabling this option for all agents results parking
496 * on the internal master.
497 *
498 * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
499 * PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
500 * PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
501 * PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
502 * PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
503 * PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
504 * PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
505 * Returns: true
506 *********************************************************************/
507 bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
508 PCI_AGENT_PARK externalAgent0,
509 PCI_AGENT_PARK externalAgent1,
510 PCI_AGENT_PARK externalAgent2,
511 PCI_AGENT_PARK externalAgent3,
512 PCI_AGENT_PARK externalAgent4,
513 PCI_AGENT_PARK externalAgent5)
514 {
515 unsigned int regData;
516 unsigned int writeData;
517
518 GT_REG_READ (pci_arbiter_control[host], &regData);
519 writeData = (internalAgent << 14) + (externalAgent0 << 15) +
520 (externalAgent1 << 16) + (externalAgent2 << 17) +
521 (externalAgent3 << 18) + (externalAgent4 << 19) +
522 (externalAgent5 << 20);
523 regData = (regData & ~(0x7f << 14)) | writeData;
524 GT_REG_WRITE (pci_arbiter_control[host], regData);
525 return true;
526 }
527
528 /********************************************************************
529 * pciSetRegionSnoopMode - This function modifys one of the 4 regions which
530 * supports Cache Coherency in the PCI_n interface.
531 * Inputs: region - One of the four regions.
532 * snoopType - There is four optional Types:
533 * 1. No Snoop.
534 * 2. Snoop to WT region.
535 * 3. Snoop to WB region.
536 * 4. Snoop & Invalidate to WB region.
537 * baseAddress - Base Address of this region.
538 * regionLength - Region length.
539 * Returns: false if one of the parameters is wrong otherwise return true.
540 *********************************************************************/
541 bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
542 PCI_SNOOP_TYPE snoopType,
543 unsigned int baseAddress,
544 unsigned int regionLength)
545 {
546 unsigned int snoopXbaseAddress;
547 unsigned int snoopXtopAddress;
548 unsigned int data;
549 unsigned int snoopHigh = baseAddress + regionLength;
550
551 if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
552 return false;
553 snoopXbaseAddress =
554 pci_snoop_control_base_0_low[host] + 0x10 * region;
555 snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
556 if (regionLength == 0) { /* closing the region */
557 GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
558 GT_REG_WRITE (snoopXtopAddress, 0);
559 return true;
560 }
561 baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
562 data = (baseAddress >> 20) | snoopType << 12;
563 GT_REG_WRITE (snoopXbaseAddress, data);
564 snoopHigh = (snoopHigh & 0xfff00000) >> 20;
565 GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
566 return true;
567 }
568
569 /*
570 *
571 */
572
573 static int gt_read_config_dword (struct pci_controller *hose,
574 pci_dev_t dev, int offset, u32 * value)
575 {
576 int bus = PCI_BUS (dev);
577
578 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
579 *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
580 PCI_DEV (dev));
581 } else {
582 *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
583 cfg_addr, offset,
584 PCI_DEV (dev), bus);
585 }
586 return 0;
587 }
588
589 static int gt_write_config_dword (struct pci_controller *hose,
590 pci_dev_t dev, int offset, u32 value)
591 {
592 int bus = PCI_BUS (dev);
593
594 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
595 pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
596 PCI_DEV (dev), value);
597 } else {
598 pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
599 offset, PCI_DEV (dev), value,
600 bus);
601 }
602 return 0;
603 }
604
605 /*
606 *
607 */
608
609 static void gt_setup_ide (struct pci_controller *hose,
610 pci_dev_t dev, struct pci_config_table *entry)
611 {
612 static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
613 u32 bar_response, bar_value;
614 int bar;
615
616 for (bar = 0; bar < 6; bar++) {
617 pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
618 0x0);
619 pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
620 &bar_response);
621
622 pciauto_region_allocate (bar_response &
623 PCI_BASE_ADDRESS_SPACE_IO ? hose->
624 pci_io : hose->pci_mem, ide_bar[bar],
625 &bar_value);
626
627 pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
628 bar_value);
629 }
630 }
631
632 #ifndef CONFIG_P3G4
633 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
634 {
635 unsigned char pin, irq;
636
637 pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
638
639 if (pin == 1) { /* only allow INT A */
640 irq = pci_irq_swizzle[(PCI_HOST) hose->
641 cfg_addr][PCI_DEV (dev)];
642 if (irq)
643 pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
644 }
645 }
646 #endif
647
648 struct pci_config_table gt_config_table[] = {
649 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
650 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
651
652 {}
653 };
654
655 struct pci_controller pci0_hose = {
656 #ifndef CONFIG_P3G4
657 fixup_irq:gt_fixup_irq,
658 #endif
659 config_table:gt_config_table,
660 };
661
662 struct pci_controller pci1_hose = {
663 #ifndef CONFIG_P3G4
664 fixup_irq:gt_fixup_irq,
665 #endif
666 config_table:gt_config_table,
667 };
668
669 void pci_init_board (void)
670 {
671 unsigned int command;
672
673 pci0_hose.first_busno = 0;
674 pci0_hose.last_busno = 0xff;
675 local_buses[0] = pci0_hose.first_busno;
676 /* PCI memory space */
677 pci_set_region (pci0_hose.regions + 0,
678 CONFIG_SYS_PCI0_0_MEM_SPACE,
679 CONFIG_SYS_PCI0_0_MEM_SPACE,
680 CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
681
682 /* PCI I/O space */
683 pci_set_region (pci0_hose.regions + 1,
684 CONFIG_SYS_PCI0_IO_SPACE_PCI,
685 CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
686
687 pci_set_ops (&pci0_hose,
688 pci_hose_read_config_byte_via_dword,
689 pci_hose_read_config_word_via_dword,
690 gt_read_config_dword,
691 pci_hose_write_config_byte_via_dword,
692 pci_hose_write_config_word_via_dword,
693 gt_write_config_dword);
694
695 pci0_hose.region_count = 2;
696
697 pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
698
699 pci_register_hose (&pci0_hose);
700
701 #ifndef CONFIG_P3G4
702 pciArbiterEnable (PCI_HOST0);
703 pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
704 #endif
705
706 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
707 command |= PCI_COMMAND_MASTER;
708 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
709
710 pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
711
712 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
713 command |= PCI_COMMAND_MEMORY;
714 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
715
716 pci1_hose.first_busno = pci0_hose.last_busno + 1;
717 pci1_hose.last_busno = 0xff;
718 pci1_hose.current_busno = pci0_hose.current_busno;
719 local_buses[1] = pci1_hose.first_busno;
720
721 /* PCI memory space */
722 pci_set_region (pci1_hose.regions + 0,
723 CONFIG_SYS_PCI1_0_MEM_SPACE,
724 CONFIG_SYS_PCI1_0_MEM_SPACE,
725 CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
726
727 /* PCI I/O space */
728 pci_set_region (pci1_hose.regions + 1,
729 CONFIG_SYS_PCI1_IO_SPACE_PCI,
730 CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
731
732 pci_set_ops (&pci1_hose,
733 pci_hose_read_config_byte_via_dword,
734 pci_hose_read_config_word_via_dword,
735 gt_read_config_dword,
736 pci_hose_write_config_byte_via_dword,
737 pci_hose_write_config_word_via_dword,
738 gt_write_config_dword);
739
740 pci1_hose.region_count = 2;
741
742 pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
743
744 pci_register_hose (&pci1_hose);
745
746 #ifndef CONFIG_P3G4
747 pciArbiterEnable (PCI_HOST1);
748 pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
749 #endif
750
751 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
752 command |= PCI_COMMAND_MASTER;
753 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
754
755 pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
756
757 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
758 command |= PCI_COMMAND_MEMORY;
759 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
760 }
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