3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* sdram_init.c - automatic memory sizing */
28 #include <galileo/memory.h>
29 #include <galileo/pci.h>
30 #include <galileo/gt64260R.h>
38 DECLARE_GLOBAL_DATA_PTR
;
51 /* structure to store the relevant information about an sdram bank */
52 typedef struct sdram_info
{
54 uchar registered
, ecc
;
59 int size
; /* detected size, not from I2C but from dram_size() */
63 void dump_dimm_info (struct sdram_info
*d
)
65 static const char *ecc_legend
[] = { "", " Parity", " ECC" };
67 printf ("dimm%s %sDRAM: %dMibytes:\n",
69 d
->registered
? "R" : "", (d
->size
>> 20));
70 printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
71 d
->drb_size
, d
->tpar
, d
->tras_clocks
, d
->burst_len
,
77 memory_map_bank (unsigned int bankNo
,
78 unsigned int bankBase
, unsigned int bankLength
)
82 printf ("mapping bank %d at %08x - %08x\n",
83 bankNo
, bankBase
, bankBase
+ bankLength
- 1);
85 printf ("unmapping bank %d\n", bankNo
);
89 memoryMapBank (bankNo
, bankBase
, bankLength
);
96 memory_map_bank_pci (unsigned int bankNo
,
97 unsigned int bankBase
, unsigned int bankLength
)
101 for (host
= PCI_HOST0
; host
<= PCI_HOST1
; host
++) {
104 DELAYED_READ_ENABLE
|
105 AGGRESSIVE_PREFETCH
|
106 READ_LINE_AGGRESSIVE_PREFETCH
|
107 READ_MULTI_AGGRESSIVE_PREFETCH
|
108 MAX_BURST_4
| PCI_NO_SWAP
;
110 pciMapMemoryBank (host
, bankNo
, bankBase
, bankLength
);
112 pciSetRegionSnoopMode (host
, bankNo
, PCI_SNOOP_WB
, bankBase
,
115 pciSetRegionFeatures (host
, bankNo
, features
, bankBase
,
122 /* ------------------------------------------------------------------------- */
124 /* much of this code is based on (or is) the code in the pip405 port */
125 /* thanks go to the authors of said port - Josh */
129 * translate ns.ns/10 coding of SPD timing values
130 * into 10 ps unit values
132 static inline unsigned short NS10to10PS (unsigned char spd_byte
)
134 unsigned short ns
, ns10
;
136 /* isolate upper nibble */
137 ns
= (spd_byte
>> 4) & 0x0F;
138 /* isolate lower nibble */
139 ns10
= (spd_byte
& 0x0F);
141 return (ns
* 100 + ns10
* 10);
145 * translate ns coding of SPD timing values
146 * into 10 ps unit values
148 static inline unsigned short NSto10PS (unsigned char spd_byte
)
150 return (spd_byte
* 100);
153 #ifdef CONFIG_ZUMA_V2
154 static int check_dimm (uchar slot
, sdram_info_t
* info
)
156 /* assume 2 dimms, 2 banks each 256M - we dont have an
157 * dimm i2c so rely on the detection routines later */
159 memset (info
, 0, sizeof (*info
));
162 info
->banks
= 2; /* Detect later */
163 info
->registered
= 0;
164 info
->drb_size
= 32; /* 16 - 256MBit, 32 - 512MBit
165 but doesn't matter, both do same
166 thing in setup_sdram() */
168 info
->tras_clocks
= 5;
171 info
->ecc
= 0; /* Detect later */
172 #endif /* CONFIG_ECC */
176 #elif defined(CONFIG_P3G4)
178 static int check_dimm (uchar slot
, sdram_info_t
* info
)
180 memset (info
, 0, sizeof (*info
));
187 info
->registered
= 0;
190 info
->tras_clocks
= 6;
198 #else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
200 /* This code reads the SPD chip on the sdram and populates
201 * the array which is passed in with the relevant information */
202 static int check_dimm (uchar slot
, sdram_info_t
* info
)
204 uchar addr
= slot
== 0 ? DIMM0_I2C_ADDR
: DIMM1_I2C_ADDR
;
206 uchar rows
, cols
, sdram_banks
, supp_cal
, width
, cal_val
;
208 uchar trp_clocks
, trcd_clocks
;
213 tmemclk
= 1000000000 / (gd
->bus_clk
/ 100); /* in 10 ps units */
215 #ifdef CONFIG_EVB64260_750CX
217 printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
218 printf (" called with slot=%d insetad!\n", slot
);
222 DP (puts ("before i2c read\n"));
224 ret
= i2c_read (addr
, 0, 128, data
, 0);
226 DP (puts ("after i2c read\n"));
228 /* zero all the values */
229 memset (info
, 0, sizeof (*info
));
232 DP (printf ("No DIMM in slot %d [err = %x]\n", slot
, ret
));
236 /* first, do some sanity checks */
237 if (data
[2] != 0x4) {
238 printf ("Not SDRAM in slot %d\n", slot
);
242 /* get various information */
245 info
->banks
= data
[5];
246 sdram_banks
= data
[17];
247 width
= data
[13] & 0x7f;
250 ("sdram_banks: %d, banks: %d\n", sdram_banks
, info
->banks
));
252 /* check if the memory is registered */
253 if (data
[21] & (BIT1
| BIT4
))
254 info
->registered
= 1;
257 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
258 info
->ecc
= (data
[11] & 2) >> 1;
261 /* bit 1 is CL2, bit 2 is CL3 */
262 supp_cal
= (data
[18] & 0x6) >> 1;
264 /* compute the relevant clock values */
265 trp_clocks
= (NSto10PS (data
[27]) + (tmemclk
- 1)) / tmemclk
;
266 trcd_clocks
= (NSto10PS (data
[29]) + (tmemclk
- 1)) / tmemclk
;
267 info
->tras_clocks
= (NSto10PS (data
[30]) + (tmemclk
- 1)) / tmemclk
;
269 DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
270 trp_clocks
, trcd_clocks
, info
->tras_clocks
));
272 /* try a CAS latency of 3 first... */
275 if (NS10to10PS (data
[9]) <= tmemclk
)
281 if (NS10to10PS (data
[23]) <= tmemclk
)
285 DP (printf ("cal_val = %d\n", cal_val
));
287 /* bummer, did't work... */
289 DP (printf ("Couldn't find a good CAS latency\n"));
293 /* get the largest delay -- these values need to all be the same
295 info
->tpar
= cal_val
;
296 if (trp_clocks
> info
->tpar
)
297 info
->tpar
= trp_clocks
;
298 if (trcd_clocks
> info
->tpar
)
299 info
->tpar
= trcd_clocks
;
301 DP (printf ("tpar set to: %d\n", info
->tpar
));
303 #ifdef CONFIG_SYS_BROKEN_CL2
304 if (info
->tpar
== 2) {
306 DP (printf ("tpar fixed-up to: %d\n", info
->tpar
));
309 /* compute the module DRB size */
311 (((1 << (rows
+ cols
)) * sdram_banks
) * width
) / _16M
;
313 DP (printf ("drb_size set to: %d\n", info
->drb_size
));
315 /* find the burst len */
316 info
->burst_len
= data
[16] & 0xf;
317 if ((info
->burst_len
& 8) == 8) {
319 } else if ((info
->burst_len
& 4) == 4) {
328 #endif /* ! CONFIG_ZUMA_V2 */
330 static int setup_sdram_common (sdram_info_t info
[2])
333 int tpar
= 2, tras_clocks
= 5, registered
= 1, ecc
= 2;
335 if (!info
[0].banks
&& !info
[1].banks
)
339 if (info
[0].tpar
> tpar
)
341 if (info
[0].tras_clocks
> tras_clocks
)
342 tras_clocks
= info
[0].tras_clocks
;
343 if (!info
[0].registered
)
345 if (info
[0].ecc
!= 2)
350 if (info
[1].tpar
> tpar
)
352 if (info
[1].tras_clocks
> tras_clocks
)
353 tras_clocks
= info
[1].tras_clocks
;
354 if (!info
[1].registered
)
356 if (info
[1].ecc
!= 2)
360 /* SDRAM configuration */
361 tmp
= GTREGREAD (SDRAM_CONFIGURATION
);
363 /* Turn on physical interleave if both DIMMs
364 * have even numbers of banks. */
365 if ((info
[0].banks
== 0 || info
[0].banks
== 2) &&
366 (info
[1].banks
== 0 || info
[1].banks
== 2)) {
367 /* physical interleave on */
370 /* physical interleave off */
374 tmp
|= (registered
<< 17);
376 /* Use buffer 1 to return read data to the CPU
380 GT_REG_WRITE (SDRAM_CONFIGURATION
, tmp
);
381 DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION
)));
384 tmp
= (((tpar
== 3) ? 2 : 1) |
385 (((tpar
== 3) ? 2 : 1) << 2) |
386 (((tpar
== 3) ? 2 : 1) << 4) | (tras_clocks
<< 8));
392 #endif /* CONFIG_ECC */
394 GT_REG_WRITE (SDRAM_TIMING
, tmp
);
395 DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
396 GTREGREAD (SDRAM_TIMING
), tpar
, tpar
, tpar
, tras_clocks
));
398 /* SDRAM address decode register */
399 /* program this with the default value */
400 GT_REG_WRITE (SDRAM_ADDRESS_DECODE
, 0x2);
401 DP (printf ("SDRAM decode: %08x\n",
402 GTREGREAD (SDRAM_ADDRESS_DECODE
)));
407 /* sets up the GT properly with information passed in */
408 static int setup_sdram (sdram_info_t
* info
)
414 /* sanity checking */
418 /* ---------------------------- */
419 /* Program the GT with the discovered data */
421 /* bank parameters */
422 tmp
= (0xf << 16); /* leave all virt bank pages open */
424 DP (printf ("drb_size: %d\n", info
->drb_size
));
425 switch (info
->drb_size
) {
438 printf ("Error in dram size calculation\n");
442 /* SDRAM bank parameters */
443 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
444 GT_REG_WRITE (SDRAM_BANK0PARAMETERS
+ (info
->slot
* 0x8), tmp
);
445 GT_REG_WRITE (SDRAM_BANK1PARAMETERS
+ (info
->slot
* 0x8), tmp
);
447 ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info
->slot
,
448 info
->slot
* 2, (info
->slot
* 2) + 1, tmp
));
450 /* set the SDRAM configuration for each bank */
451 for (i
= info
->slot
* 2; i
< ((info
->slot
* 2) + info
->banks
); i
++) {
452 DP (printf ("*** Running a MRS cycle for bank %d ***\n", i
));
455 memory_map_bank (i
, 0, GB
/ 4);
458 GT_REG_WRITE (SDRAM_OPERATION_MODE
, 0x3);
459 check
= GTREGREAD (SDRAM_OPERATION_MODE
);
464 /* wait for the command to complete */
465 while ((GTREGREAD (SDRAM_OPERATION_MODE
) & (1 << 31)) == 0);
467 /* switch back to normal operation mode */
468 GT_REG_WRITE (SDRAM_OPERATION_MODE
, 0);
469 check
= GTREGREAD (SDRAM_OPERATION_MODE
);
472 memory_map_bank (i
, 0, 0);
473 DP (printf ("*** MRS cycle for bank %d done ***\n", i
));
480 * Check memory range for valid RAM. A simple memory test determines
481 * the actually available RAM size between addresses `base' and
482 * `base + maxsize'. Some (not all) hardware errors are detected:
483 * - short between address lines
484 * - short between data lines
486 static long int dram_size (long int *base
, long int maxsize
)
488 volatile long int *addr
, *b
= base
;
489 long int cnt
, val
, save1
, save2
;
491 #define STARTVAL (1<<20) /* start test at 1M */
492 for (cnt
= STARTVAL
/ sizeof (long); cnt
< maxsize
/ sizeof (long);
494 addr
= base
+ cnt
; /* pointer arith! */
496 save1
= *addr
; /* save contents of addr */
497 save2
= *b
; /* save contents of base */
499 *addr
= cnt
; /* write cnt to addr */
500 *b
= 0; /* put null at base */
502 /* check at base address */
504 *addr
= save1
; /* restore *addr */
505 *b
= save2
; /* restore *b */
508 val
= *addr
; /* read *addr */
514 /* fix boundary condition.. STARTVAL means zero */
515 if (cnt
== STARTVAL
/ sizeof (long))
517 return (cnt
* sizeof (long));
523 /* ------------------------------------------------------------------------- */
525 /* U-Boot interface function to SDRAM init - this is where all the
526 * controlling logic happens */
527 phys_size_t
initdram (int board_type
)
529 ulong checkbank
[4] = {[0 ... 3] = 0 };
533 sdram_info_t dimm_info
[2];
536 /* first, use the SPD to get info about the SDRAM */
538 /* check the NHR bit and skip mem init if it's already done */
539 nhr
= get_hid0 () & (1 << 16);
542 printf ("Skipping SDRAM setup due to NHR bit being set\n");
545 check_dimm (0, &dimm_info
[0]);
548 #ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
549 check_dimm (1, &dimm_info
[1]);
550 #else /* CONFIG_EVB64260_750CX */
551 memset (&dimm_info
[1], 0, sizeof (sdram_info_t
));
554 /* unmap all banks */
555 memory_map_bank (0, 0, 0);
556 memory_map_bank (1, 0, 0);
557 memory_map_bank (2, 0, 0);
558 memory_map_bank (3, 0, 0);
560 /* Now, program the GT with the correct values */
561 if (setup_sdram_common (dimm_info
)) {
562 printf ("Setup common failed.\n");
565 if (setup_sdram (&dimm_info
[0])) {
566 printf ("Setup for DIMM1 failed.\n");
569 if (setup_sdram (&dimm_info
[1])) {
570 printf ("Setup for DIMM2 failed.\n");
573 /* set the NHR bit */
574 set_hid0 (get_hid0 () | (1 << 16));
576 /* next, size the SDRAM banks */
579 if (dimm_info
[0].banks
> 0)
581 if (dimm_info
[0].banks
> 1)
583 if (dimm_info
[0].banks
> 2)
584 printf ("Error, SPD claims DIMM1 has >2 banks\n");
586 if (dimm_info
[1].banks
> 0)
588 if (dimm_info
[1].banks
> 1)
590 if (dimm_info
[1].banks
> 2)
591 printf ("Error, SPD claims DIMM2 has >2 banks\n");
593 /* Generic dram sizer: works even if we don't have i2c DIMMs,
594 * as long as the timing settings are more or less correct */
597 * pass 1: size all the banks, using first bat (0-256M)
598 * limitation: we only support 256M per bank due to
599 * us only having 1 BAT for all DRAM
601 for (bank_no
= 0; bank_no
< CONFIG_SYS_DRAM_BANKS
; bank_no
++) {
602 /* skip over banks that are not populated */
603 if (!checkbank
[bank_no
])
606 DP (printf ("checking bank %d\n", bank_no
));
608 memory_map_bank (bank_no
, 0, GB
/ 4);
609 checkbank
[bank_no
] = dram_size (NULL
, GB
/ 4);
610 memory_map_bank (bank_no
, 0, 0);
612 DP (printf ("bank %d %08lx\n", bank_no
, checkbank
[bank_no
]));
616 * pass 2: contiguously map each bank into physical address
619 dimm_info
[0].banks
= dimm_info
[1].banks
= 0;
620 for (bank_no
= 0; bank_no
< CONFIG_SYS_DRAM_BANKS
; bank_no
++) {
621 if (!checkbank
[bank_no
])
624 dimm_info
[bank_no
/ 2].banks
++;
625 dimm_info
[bank_no
/ 2].size
+= checkbank
[bank_no
];
627 memory_map_bank (bank_no
, total
, checkbank
[bank_no
]);
629 memory_map_bank_pci (bank_no
, total
, checkbank
[bank_no
]);
631 total
+= checkbank
[bank_no
];
635 #ifdef CONFIG_ZUMA_V2
637 * We always enable ECC when bank 2 and 3 are unpopulated
638 * If we 2 or 3 are populated, we CAN'T support ECC.
639 * (Zuma boards only support ECC in banks 0 and 1; assume that
640 * in that configuration, ECC chips are mounted, even for stacked
643 if (checkbank
[2] == 0 && checkbank
[3] == 0) {
644 dimm_info
[0].ecc
= 2;
645 GT_REG_WRITE (SDRAM_TIMING
,
646 GTREGREAD (SDRAM_TIMING
) | (1 << 13));
647 /* TODO: do we have to run MRS cycles again? */
649 #endif /* CONFIG_ZUMA_V2 */
651 if (GTREGREAD (SDRAM_TIMING
) & (1 << 13)) {
654 #endif /* CONFIG_ECC */
657 dump_dimm_info (&dimm_info
[0]);
658 dump_dimm_info (&dimm_info
[1]);
660 /* TODO: return at MOST 256M? */
661 /* return total > GB/4 ? GB/4 : total; */