board/fads/fads.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
   6  * and Dan Malek
   7  *
   8  * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
   9  *
  10  * This header file contains values common to all FADS family boards.
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 /****************************************************************************
  32  * Flash Memory Map as used by U-Boot:
  33  *
  34  *                          Start Address    Length
  35  * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
  36  * |                       | 0xFE00_0100     Reset Vector
  37  * +                       + 0xFE0?_????
  38  * | U-Boot code           |
  39  * |                       |
  40  * +-----------------------+ 0xFE04_0000 (sector border)
  41  * |                       |
  42  * |                       |
  43  * | U-Boot environment    |
  44  * |                       |                                 ^
  45  * |                       |                                 | U-Boot
  46  * +=======================+ 0xFE08_0000 (sector border)    -----------------
  47  * | Available             |                                 | Applications
  48  * | ...                   |                                 v
  49  *
  50  *****************************************************************************/
  51
  52 #if 0
  53 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  54 #else
  55 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  56 #endif
  57
  58 #define CONFIG_ENV_OVERWRITE
  59
  60 #define CONFIG_NFSBOOTCOMMAND                                                   \
  61     "dhcp;"                                                                     \
  62     "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "                       \
  63     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  64     "bootm"
  65
  66 #define CONFIG_BOOTCOMMAND                                                      \
  67     "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
  68     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  69     "bootm fe080000"
  70
  71 #undef CONFIG_BOOTARGS
  72
  73 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  74 #define CONFIG_BZIP2     /* include support for bzip2 compressed images */
  75
  76 /*
  77  * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
  78  * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
  79  * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
  80  * got FEC so FEC is the default.
  81  */
  82 #ifndef CONFIG_ADS
  83 #undef  CONFIG_SCC1_ENET                /* Disable SCC1 ethernet */
  84 #define CONFIG_FEC_ENET                 /* Use FEC ethernet  */
  85 #else                                   /* Old ADS has not got FEC option */
  86 #define CONFIG_SCC1_ENET                /* Use SCC1 ethernet */
  87 #undef  CONFIG_FEC_ENET                 /* No FEC ethernet  */
  88 #endif /* !CONFIG_ADS */
  89
  90 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
  91 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
  92 #endif
  93
  94 #ifdef CONFIG_FEC_ENET
  95 #define CFG_DISCOVER_PHY
  96 #endif
  97
  98
  99 /*
 100  * BOOTP options
 101  */
 102 #define CONFIG_BOOTP_BOOTFILESIZE
 103 #define CONFIG_BOOTP_BOOTPATH
 104 #define CONFIG_BOOTP_GATEWAY
 105 #define CONFIG_BOOTP_HOSTNAME
 106
 107
 108 #if !defined(FADS_COMMANDS_ALREADY_DEFINED)
 109 /*
 110  * Command line configuration.
 111  */
 112 #include <config_cmd_default.h>
 113
 114 #define CONFIG_CMD_ASKENV
 115 #define CONFIG_CMD_DHCP
 116 #define CONFIG_CMD_ECHO
 117 #define CONFIG_CMD_IMMAP
 118 #define CONFIG_CMD_JFFS2
 119 #define CONFIG_CMD_MII
 120 #define CONFIG_CMD_PCMCIA
 121 #define CONFIG_CMD_PING
 122
 123 #endif
 124
 125
 126 /*
 127  * Miscellaneous configurable options
 128  */
 129 #define CFG_PROMPT              "=>"            /* Monitor Command Prompt       */
 130 #define CFG_HUSH_PARSER
 131 #define CFG_PROMPT_HUSH_PS2     "> "
 132 #define CFG_LONGHELP                            /* #undef to save memory        */
 133 #if defined(CONFIG_CMD_KGDB)
 134 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
 135 #else
 136 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 137 #endif
 138 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size  */
 139 #define CFG_MAXARGS             16              /* max number of command args   */
 140 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 141
 142 #define CFG_LOAD_ADDR           0x00100000
 143
 144 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 145
 146 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 147
 148 /*
 149  * Low Level Configuration Settings
 150  * (address mappings, register initial values, etc.)
 151  * You should know what you are doing if you make changes here.
 152  */
 153
 154 /*-----------------------------------------------------------------------
 155  * Internal Memory Mapped Register
 156  */
 157 #define CFG_IMMR                0xFF000000
 158
 159 /*-----------------------------------------------------------------------
 160  * Definitions for initial stack pointer and data area (in DPRAM)
 161  */
 162 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 163 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 164 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 165 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 166 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 167
 168 /*-----------------------------------------------------------------------
 169  * Start addresses for the final memory configuration
 170  * (Set up by the startup code)
 171  * Please note that CFG_SDRAM_BASE _must_ start at 0
 172  */
 173 #define CFG_SDRAM_BASE          0x00000000
 174 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
 175 #define CFG_SDRAM_SIZE          0x00800000              /* 8 Mbyte */
 176 /*
 177  * 2048 SDRAM rows
 178  * 1000 factor s -> ms
 179  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 180  * 4    Number of refresh cycles per period
 181  * 64   Refresh cycle in ms per number of rows
 182  */
 183 #define CFG_PTA_PER_CLK         ((2048 * 64 * 1000) / (4 * 64))
 184 #elif defined(CONFIG_FADS)                              /* Old/new FADS */
 185 #define CFG_SDRAM_SIZE          0x00400000              /* 4 Mbyte */
 186 #else                                                   /* Old ADS */
 187 #define CFG_SDRAM_SIZE          0x00000000              /* No SDRAM */
 188 #endif
 189
 190 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 191 #if (CFG_SDRAM_SIZE)
 192 #define CFG_MEMTEST_END         CFG_SDRAM_SIZE  /* 1 ... SDRAM_SIZE     */
 193 #else
 194 #define CFG_MEMTEST_END         0x0400000       /* 1 ... 4 MB in DRAM   */
 195 #endif /* CFG_SDRAM_SIZE */
 196
 197 /*
 198  * For booting Linux, the board info and command line data
 199  * have to be in the first 8 MB of memory, since this is
 200  * the maximum mapped by the Linux kernel during initialization.
 201  */
 202 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 203
 204 #define CFG_MONITOR_BASE        TEXT_BASE
 205 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 KB for monitor   */
 206
 207 #ifdef CONFIG_BZIP2
 208 #define CFG_MALLOC_LEN          (2500 << 10)    /* Reserve ~2.5 MB for malloc() */
 209 #else
 210 #define CFG_MALLOC_LEN          (384 << 10)     /* Reserve 384 kB for malloc()  */
 211 #endif /* CONFIG_BZIP2 */
 212
 213 /*-----------------------------------------------------------------------
 214  * Flash organization
 215  */
 216 #define CFG_FLASH_BASE          CFG_MONITOR_BASE
 217 #define CFG_FLASH_SIZE          ((uint)(8 * 1024 * 1024))       /* max 8Mbyte   */
 218
 219 #define CFG_MAX_FLASH_BANKS     4       /* max number of memory banks           */
 220 #define CFG_MAX_FLASH_SECT      8       /* max number of sectors on one chip    */
 221
 222 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 223 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 224
 225 #define CFG_ENV_IS_IN_FLASH     1
 226 #define CFG_ENV_SECT_SIZE       0x40000 /* see README - env sector total size   */
 227 #define CFG_ENV_OFFSET          CFG_ENV_SECT_SIZE
 228 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment            */
 229
 230 #define CFG_DIRECT_FLASH_TFTP
 231
 232 #if defined(CONFIG_CMD_JFFS2)
 233
 234 /*
 235  * JFFS2 partitions
 236  *
 237  */
 238 /* No command line, one static partition, whole device */
 239 #undef CONFIG_JFFS2_CMDLINE
 240 #define CONFIG_JFFS2_DEV                "nor0"
 241 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 242 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 243
 244 /* mtdparts command line support */
 245 /* Note: fake mtd_id used, no linux mtd map file */
 246 /*
 247 #define CONFIG_JFFS2_CMDLINE
 248 #define MTDIDS_DEFAULT          "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
 249 #define MTDPARTS_DEFAULT        "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
 250 */
 251
 252 #define CFG_JFFS2_SORT_FRAGMENTS
 253 #endif
 254
 255 /*-----------------------------------------------------------------------
 256  * Cache Configuration
 257  */
 258 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 259 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 260
 261 /*-----------------------------------------------------------------------
 262  * I2C configuration
 263  */
 264 #if defined(CONFIG_CMD_I2C)
 265 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 266 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address defaults */
 267 #define CFG_I2C_SLAVE           0x7F
 268 #endif
 269
 270 /*-----------------------------------------------------------------------
 271  * SYPCR - System Protection Control                            11-9
 272  * SYPCR can only be written once after reset!
 273  *-----------------------------------------------------------------------
 274  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 275  */
 276 #if defined(CONFIG_WATCHDOG)
 277 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 278                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 279 #else
 280 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 281 #endif
 282
 283 /*-----------------------------------------------------------------------
 284  * SIUMCR - SIU Module Configuration                            11-6
 285  *-----------------------------------------------------------------------
 286  * PCMCIA config., multi-function pin tri-state
 287  */
 288 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 289
 290 /*-----------------------------------------------------------------------
 291  * TBSCR - Time Base Status and Control                         11-26
 292  *-----------------------------------------------------------------------
 293  * Clear Reference Interrupt Status, Timebase freezing enabled
 294  */
 295 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 296
 297 /*-----------------------------------------------------------------------
 298  * PISCR - Periodic Interrupt Status and Control                11-31
 299  *-----------------------------------------------------------------------
 300  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 301  */
 302 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 303
 304 /*-----------------------------------------------------------------------
 305  * SCCR - System Clock and reset Control Register               15-27
 306  *-----------------------------------------------------------------------
 307  * Set clock output, timebase and RTC source and divider,
 308  * power management and some other internal clocks
 309  */
 310 #define SCCR_MASK       SCCR_EBDF11
 311 #define CFG_SCCR        SCCR_TBS
 312
 313 /*-----------------------------------------------------------------------
 314  * DER - Debug Enable Register
 315  *-----------------------------------------------------------------------
 316  * Set to zero to prevent the processor from entering debug mode
 317  */
 318 #define CFG_DER          0
 319
 320 /* Because of the way the 860 starts up and assigns CS0 the entire
 321  * address space, we have to set the memory controller differently.
 322  * Normally, you write the option register first, and then enable the
 323  * chip select by writing the base register.  For CS0, you must write
 324  * the base register first, followed by the option register.
 325  */
 326
 327 /*
 328  * Init Memory Controller:
 329  *
 330  * BR0/OR0 (Flash)
 331  * BR1/OR1 (BCSR)
 332  */
 333 /* the other CS:s are determined by looking at parameters in BCSRx */
 334
 335 #define BCSR_ADDR               ((uint) 0xFF080000)
 336
 337 #define CFG_PRELIM_OR_AM        0xFF800000      /* OR addr mask */
 338
 339 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
 340 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 341
 342 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
 343 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
 344
 345 /* BCSRx - Board Control and Status Registers */
 346 #define CFG_OR1_PRELIM  0xFFFF8110              /* 64Kbyte address space */
 347 #define CFG_BR1_PRELIM  ((BCSR_ADDR) | BR_V)
 348
 349 /*
 350  * Internal Definitions
 351  *
 352  * Boot Flags
 353  */
 354 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 355 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 356
 357 /* values according to the manual */
 358
 359 #define BCSR0                   ((uint) (BCSR_ADDR + 0x00))
 360 #define BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 361 #define BCSR2                   ((uint) (BCSR_ADDR + 0x08))
 362 #define BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
 363 #define BCSR4                   ((uint) (BCSR_ADDR + 0x10))
 364
 365 /*
 366  * (F)ADS bitvalues by Helmut Buchsbaum
 367  *
 368  * See User's Manual for a proper
 369  * description of the following structures
 370  */
 371
 372 #define BCSR0_ERB       ((uint)0x80000000)
 373 #define BCSR0_IP        ((uint)0x40000000)
 374 #define BCSR0_BDIS      ((uint)0x10000000)
 375 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 376 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 377 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 378 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 379 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 380
 381 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 382 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 383 #define BCSR1_ETHEN              ((uint)0x20000000)
 384 #define BCSR1_IRDEN              ((uint)0x10000000)
 385 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 386 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 387 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 388 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 389 #define BCSR1_PCCEN              ((uint)0x00800000)
 390 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 391 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 392 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 393 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 394 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 395 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 396
 397 #define BCSR1_PCCVCCON           BCSR1_PCCVCC0
 398
 399 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 400 #define BCSR2_FLASH_PD_SHIFT     28
 401 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 402 #define BCSR2_DRAM_PD_SHIFT      23
 403 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 404 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 405
 406 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 407 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 408 #define BCSR3_BREVNR0            ((ushort)0x0080)
 409 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 410 #define BCSR3_BREVN1             ((ushort)0x0008)
 411 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 412
 413 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 414 #define BCSR4_TFPLDL             ((uint)0x40000000)
 415 #define BCSR4_TPSQEL             ((uint)0x20000000)
 416 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 417 #if defined(CONFIG_MPC823)
 418 #define BCSR4_USB_EN             ((uint)0x08000000)
 419 #define BCSR4_USB_SPEED          ((uint)0x04000000)
 420 #define BCSR4_VCCO               ((uint)0x02000000)
 421 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
 422 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
 423 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
 424 #define BCSR4_MODEM_EN           ((uint)0x00100000)
 425 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 426 #elif defined(CONFIG_MPC850)
 427 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 428 #elif defined(CONFIG_MPC860SAR)
 429 #define BCSR4_UTOPIA_EN          ((uint)0x08000000)
 430 #else /* MPC860T and other chips with FEC */
 431 #define BCSR4_FETH_EN            ((uint)0x08000000)
 432 #define BCSR4_FETHCFG0           ((uint)0x04000000)
 433 #define BCSR4_FETHFDE            ((uint)0x02000000)
 434 #define BCSR4_FETHCFG1           ((uint)0x00400000)
 435 #define BCSR4_FETHRST            ((uint)0x00200000)
 436 #endif
 437
 438 /* BSCR5 exists on MPC86xADS and MPC885ADS only */
 439
 440 #define CFG_PHYDEV_ADDR         (BCSR_ADDR + 0x20000)
 441
 442 #define BCSR5                   (CFG_PHYDEV_ADDR + 0x300)
 443
 444 #define BCSR5_MII2_EN           0x40
 445 #define BCSR5_MII2_RST          0x20
 446 #define BCSR5_T1_RST            0x10
 447 #define BCSR5_ATM155_RST        0x08
 448 #define BCSR5_ATM25_RST         0x04
 449 #define BCSR5_MII1_EN           0x02
 450 #define BCSR5_MII1_RST          0x01
 451
 452 /* We don't use the 8259.
 453 */
 454 #define NR_8259_INTS    0
 455
 456 /* Machine type
 457 */
 458 #define _MACH_8xx (_MACH_fads)
 459
 460 /*-----------------------------------------------------------------------
 461  * PCMCIA stuff
 462  *-----------------------------------------------------------------------
 463  */
 464 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 465 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 466 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 467 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 468 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 469 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 470 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 471 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 472
 473 /*-----------------------------------------------------------------------
 474  * IDE/ATA stuff
 475  *-----------------------------------------------------------------------
 476  */
 477 #define CONFIG_MAC_PARTITION    1
 478 #define CONFIG_DOS_PARTITION    1
 479 #define CONFIG_ISO_PARTITION    1
 480
 481 #undef  CONFIG_ATAPI
 482 #if 0   /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
 483 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 484 #endif
 485 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 486 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 487 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 488
 489 #define CFG_IDE_MAXBUS          1       /* max. 2 IDE busses    */
 490 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 491
 492 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 493 #define CFG_ATA_IDE0_OFFSET     0x0000
 494
 495 /* Offset for data I/O                  */
 496 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 497 /* Offset for normal register accesses  */
 498 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 499 /* Offset for alternate registers       */
 500 #define CFG_ATA_ALT_OFFSET      0x0000
 501
 502 #define CONFIG_DISK_SPINUP_TIME 1000000
 503 /* #undef CONFIG_DISK_SPINUP_TIME */    /* usin  Compact Flash */