2 * Copyright 2004, 2011 Freescale Semiconductor.
4 * SPDX-License-Identifier: GPL-2.0+
12 * CADMUS Board System Registers
14 #ifndef CONFIG_SYS_CADMUS_BASE_REG
15 #define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
18 typedef struct cadmus_reg
{
19 u_char cm_ver
; /* Board version */
20 u_char cm_csr
; /* General control/status */
21 u_char cm_rst
; /* Reset control */
22 u_char cm_hsclk
; /* High speed clock */
23 u_char cm_hsxclk
; /* High speed clock extended */
24 u_char cm_led
; /* LED data */
25 u_char cm_pci
; /* PCI control/status */
26 u_char cm_dma
; /* DMA control */
27 u_char cm_reserved
[248]; /* Total 256 bytes */
32 get_board_version(void)
34 volatile cadmus_reg_t
*cadmus
= (cadmus_reg_t
*)CONFIG_SYS_CADMUS_BASE_REG
;
36 return cadmus
->cm_ver
;
43 volatile cadmus_reg_t
*cadmus
= (cadmus_reg_t
*)CONFIG_SYS_CADMUS_BASE_REG
;
45 uint pci1_speed
= (cadmus
->cm_pci
>> 2) & 0x3; /* PSPEED in [4:5] */
47 if (pci1_speed
== 0) {
49 } else if (pci1_speed
== 1) {
52 /* Really, unknown. Be safe? */
61 volatile cadmus_reg_t
*cadmus
= (cadmus_reg_t
*)CONFIG_SYS_CADMUS_BASE_REG
;
64 * PCI slot in USER bits CSR[6:7] by convention.
66 return ((cadmus
->cm_csr
>> 6) & 0x3) + 1;
73 volatile cadmus_reg_t
*cadmus
= (cadmus_reg_t
*)CONFIG_SYS_CADMUS_BASE_REG
;
76 * PCI DUAL in CM_PCI[3]
78 return cadmus
->cm_pci
& 0x10;