board/freescale/ls1043aqds/ls1043aqds.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/fdt.h>
  14 #include <asm/arch/soc.h>
  15 #include <ahci.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <scsi.h>
  19 #include <fm_eth.h>
  20 #include <fsl_csu.h>
  21 #include <fsl_esdhc.h>
  22 #include <fsl_ifc.h>
  23 #include <spl.h>
  24
  25 #include "../common/qixis.h"
  26 #include "ls1043aqds_qixis.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 enum {
  31         MUX_TYPE_GPIO,
  32 };
  33
  34 /* LS1043AQDS serdes mux */
  35 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  36 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  37 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  38 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  39 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  40 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  41 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  42 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  43 #define CFG_UART_MUX_MASK       0x6
  44 #define CFG_UART_MUX_SHIFT      1
  45 #define CFG_LPUART_EN           0x1
  46
  47 int checkboard(void)
  48 {
  49         char buf[64];
  50 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  51         u8 sw;
  52 #endif
  53
  54         puts("Board: LS1043AQDS, boot from ");
  55
  56 #ifdef CONFIG_SD_BOOT
  57         puts("SD\n");
  58 #elif defined(CONFIG_QSPI_BOOT)
  59         puts("QSPI\n");
  60 #else
  61         sw = QIXIS_READ(brdcfg[0]);
  62         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  63
  64         if (sw < 0x8)
  65                 printf("vBank: %d\n", sw);
  66         else if (sw == 0x8)
  67                 puts("PromJet\n");
  68         else if (sw == 0x9)
  69                 puts("NAND\n");
  70         else if (sw == 0x15)
  71                 printf("IFCCard\n");
  72         else
  73                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  74 #endif
  75
  76         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  77                QIXIS_READ(id), QIXIS_READ(arch));
  78
  79         printf("FPGA:  v%d (%s), build %d\n",
  80                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  81                (int)qixis_read_minor());
  82
  83         return 0;
  84 }
  85
  86 bool if_board_diff_clk(void)
  87 {
  88         u8 diff_conf = QIXIS_READ(brdcfg[11]);
  89
  90         return diff_conf & 0x40;
  91 }
  92
  93 unsigned long get_board_sys_clk(void)
  94 {
  95         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  96
  97         switch (sysclk_conf & 0x0f) {
  98         case QIXIS_SYSCLK_64:
  99                 return 64000000;
 100         case QIXIS_SYSCLK_83:
 101                 return 83333333;
 102         case QIXIS_SYSCLK_100:
 103                 return 100000000;
 104         case QIXIS_SYSCLK_125:
 105                 return 125000000;
 106         case QIXIS_SYSCLK_133:
 107                 return 133333333;
 108         case QIXIS_SYSCLK_150:
 109                 return 150000000;
 110         case QIXIS_SYSCLK_160:
 111                 return 160000000;
 112         case QIXIS_SYSCLK_166:
 113                 return 166666666;
 114         }
 115
 116         return 66666666;
 117 }
 118
 119 unsigned long get_board_ddr_clk(void)
 120 {
 121         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 122
 123         if (if_board_diff_clk())
 124                 return get_board_sys_clk();
 125         switch ((ddrclk_conf & 0x30) >> 4) {
 126         case QIXIS_DDRCLK_100:
 127                 return 100000000;
 128         case QIXIS_DDRCLK_125:
 129                 return 125000000;
 130         case QIXIS_DDRCLK_133:
 131                 return 133333333;
 132         }
 133
 134         return 66666666;
 135 }
 136
 137 int select_i2c_ch_pca9547(u8 ch)
 138 {
 139         int ret;
 140
 141         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 142         if (ret) {
 143                 puts("PCA: failed to select proper channel\n");
 144                 return ret;
 145         }
 146
 147         return 0;
 148 }
 149
 150 int dram_init(void)
 151 {
 152         /*
 153          * When resuming from deep sleep, the I2C channel may not be
 154          * in the default channel. So, switch to the default channel
 155          * before accessing DDR SPD.
 156          */
 157         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 158         gd->ram_size = initdram(0);
 159
 160         return 0;
 161 }
 162
 163 int i2c_multiplexer_select_vid_channel(u8 channel)
 164 {
 165         return select_i2c_ch_pca9547(channel);
 166 }
 167
 168 void board_retimer_init(void)
 169 {
 170         u8 reg;
 171
 172         /* Retimer is connected to I2C1_CH7_CH5 */
 173         reg = I2C_MUX_CH7;
 174         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
 175         reg = I2C_MUX_CH5;
 176         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 177
 178         /* Access to Control/Shared register */
 179         reg = 0x0;
 180         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 181
 182         /* Read device revision and ID */
 183         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 184         debug("Retimer version id = 0x%x\n", reg);
 185
 186         /* Enable Broadcast. All writes target all channel register sets */
 187         reg = 0x0c;
 188         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 189
 190         /* Reset Channel Registers */
 191         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 192         reg |= 0x4;
 193         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 194
 195         /* Enable override divider select and Enable Override Output Mux */
 196         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 197         reg |= 0x24;
 198         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 199
 200         /* Select VCO Divider to full rate (000) */
 201         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 202         reg &= 0x8f;
 203         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 204
 205         /* Selects active PFD MUX Input as Re-timed Data (001) */
 206         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 207         reg &= 0x3f;
 208         reg |= 0x20;
 209         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 210
 211         /* Set data rate as 10.3125 Gbps */
 212         reg = 0x0;
 213         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 214         reg = 0xb2;
 215         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 216         reg = 0x90;
 217         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 218         reg = 0xb3;
 219         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 220         reg = 0xcd;
 221         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 222 }
 223
 224 int board_early_init_f(void)
 225 {
 226 #ifdef CONFIG_LPUART
 227         u8 uart;
 228 #endif
 229         fsl_lsch2_early_init_f();
 230 #ifdef CONFIG_LPUART
 231         /* We use lpuart0 as system console */
 232         uart = QIXIS_READ(brdcfg[14]);
 233         uart &= ~CFG_UART_MUX_MASK;
 234         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 235         QIXIS_WRITE(brdcfg[14], uart);
 236 #endif
 237
 238         return 0;
 239 }
 240
 241 #ifdef CONFIG_FSL_DEEP_SLEEP
 242 /* determine if it is a warm boot */
 243 bool is_warm_boot(void)
 244 {
 245 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 246         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 247
 248         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 249                 return 1;
 250
 251         return 0;
 252 }
 253 #endif
 254
 255 int config_board_mux(int ctrl_type)
 256 {
 257         u8 reg14;
 258
 259         reg14 = QIXIS_READ(brdcfg[14]);
 260
 261         switch (ctrl_type) {
 262         case MUX_TYPE_GPIO:
 263                 reg14 = (reg14 & (~0x30)) | 0x20;
 264                 break;
 265         default:
 266                 puts("Unsupported mux interface type\n");
 267                 return -1;
 268         }
 269
 270         QIXIS_WRITE(brdcfg[14], reg14);
 271
 272         return 0;
 273 }
 274
 275 int config_serdes_mux(void)
 276 {
 277         return 0;
 278 }
 279
 280
 281 #ifdef CONFIG_MISC_INIT_R
 282 int misc_init_r(void)
 283 {
 284         if (hwconfig("gpio"))
 285                 config_board_mux(MUX_TYPE_GPIO);
 286
 287         return 0;
 288 }
 289 #endif
 290
 291 int board_init(void)
 292 {
 293         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
 294                                    CONFIG_SYS_CCI400_ADDR;
 295
 296         /* Set CCI-400 control override register to enable barrier
 297          * transaction */
 298         out_le32(&cci->ctrl_ord,
 299                  CCI400_CTRLORD_EN_BARRIER);
 300
 301         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 302         board_retimer_init();
 303
 304 #ifdef CONFIG_SYS_FSL_SERDES
 305         config_serdes_mux();
 306 #endif
 307
 308 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 309         enable_layerscape_ns_access();
 310 #endif
 311
 312 #ifdef CONFIG_ENV_IS_NOWHERE
 313         gd->env_addr = (ulong)&default_environment[0];
 314 #endif
 315         return 0;
 316 }
 317
 318 #ifdef CONFIG_OF_BOARD_SETUP
 319 int ft_board_setup(void *blob, bd_t *bd)
 320 {
 321         u64 base[CONFIG_NR_DRAM_BANKS];
 322         u64 size[CONFIG_NR_DRAM_BANKS];
 323
 324         /* fixup DT for the two DDR banks */
 325         base[0] = gd->bd->bi_dram[0].start;
 326         size[0] = gd->bd->bi_dram[0].size;
 327         base[1] = gd->bd->bi_dram[1].start;
 328         size[1] = gd->bd->bi_dram[1].size;
 329
 330         fdt_fixup_memory_banks(blob, base, size, 2);
 331         ft_cpu_setup(blob, bd);
 332
 333 #ifdef CONFIG_SYS_DPAA_FMAN
 334         fdt_fixup_fman_ethernet(blob);
 335         fdt_fixup_board_enet(blob);
 336 #endif
 337         return 0;
 338 }
 339 #endif
 340
 341 u8 flash_read8(void *addr)
 342 {
 343         return __raw_readb(addr + 1);
 344 }
 345
 346 void flash_write16(u16 val, void *addr)
 347 {
 348         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 349
 350         __raw_writew(shftval, addr);
 351 }
 352
 353 u16 flash_read16(void *addr)
 354 {
 355         u16 val = __raw_readw(addr);
 356
 357         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 358 }