board/freescale/ls2080ardb/eth_ls2080rdb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <netdev.h>
  11 #include <malloc.h>
  12 #include <fsl_mdio.h>
  13 #include <miiphy.h>
  14 #include <phy.h>
  15 #include <fm_eth.h>
  16 #include <asm/io.h>
  17 #include <exports.h>
  18 #include <asm/arch/fsl_serdes.h>
  19 #include <fsl-mc/ldpaa_wriop.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int board_eth_init(bd_t *bis)
  24 {
  25 #if defined(CONFIG_FSL_MC_ENET)
  26         int i, interface;
  27         struct memac_mdio_info mdio_info;
  28         struct mii_dev *dev;
  29         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  30         u32 srds_s1;
  31         struct memac_mdio_controller *reg;
  32
  33         srds_s1 = in_le32(&gur->rcwsr[28]) &
  34                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  35         srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  36
  37         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  38         mdio_info.regs = reg;
  39         mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  40
  41         /* Register the EMI 1 */
  42         fm_memac_mdio_init(bis, &mdio_info);
  43
  44         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  45         mdio_info.regs = reg;
  46         mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  47
  48         /* Register the EMI 2 */
  49         fm_memac_mdio_init(bis, &mdio_info);
  50
  51         switch (srds_s1) {
  52         case 0x2A:
  53                 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
  54                 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
  55                 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
  56                 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
  57                 wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
  58                 wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
  59                 wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
  60                 wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
  61
  62                 break;
  63         default:
  64                 printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
  65                        srds_s1);
  66                 break;
  67         }
  68
  69         for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
  70                 interface = wriop_get_enet_if(i);
  71                 switch (interface) {
  72                 case PHY_INTERFACE_MODE_XGMII:
  73                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  74                         wriop_set_mdio(i, dev);
  75                         break;
  76                 default:
  77                         break;
  78                 }
  79         }
  80
  81         for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
  82                 switch (wriop_get_enet_if(i)) {
  83                 case PHY_INTERFACE_MODE_XGMII:
  84                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  85                         wriop_set_mdio(i, dev);
  86                         break;
  87                 default:
  88                         break;
  89                 }
  90         }
  91
  92         cpu_eth_init(bis);
  93 #endif /* CONFIG_FMAN_ENET */
  94
  95 #ifdef CONFIG_PHY_AQUANTIA
  96         /*
  97          * Export functions to be used by AQ firmware
  98          * upload application
  99          */
 100         gd->jt->strcpy = strcpy;
 101         gd->jt->mdelay = mdelay;
 102         gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 103         gd->jt->phy_find_by_mask = phy_find_by_mask;
 104         gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 105         gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 106 #endif
 107         return pci_eth_init(bis);
 108 }