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rename CFG_ macros to CONFIG_SYS
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1 /*
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <asm/fec.h>
26 #include <asm/immap.h>
27
28 #include <config.h>
29 #include <net.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
34 #undef MII_DEBUG
35 #undef ET_DEBUG
36
37 int fecpin_setclear(struct eth_device *dev, int setclear)
38 {
39 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
40
41 if (setclear) {
42 gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
43 } else {
44 }
45 return 0;
46 }
47
48 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
49 #include <miiphy.h>
50
51 /* Make MII read/write commands for the FEC. */
52 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
53
54 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
55
56 /* PHY identification */
57 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
58 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
59 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
60 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
61 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
62 #define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
63 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
64 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
65 #define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
66 #define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
67
68 #define STR_ID_LXT970 "LXT970"
69 #define STR_ID_LXT971 "LXT971"
70 #define STR_ID_82555 "Intel82555"
71 #define STR_ID_QS6612 "QS6612"
72 #define STR_ID_AMD79C784 "AMD79C784"
73 #define STR_ID_AMD79C874VC "AMD79C874VC"
74 #define STR_ID_LSI80225 "LSI80225"
75 #define STR_ID_LSI80225B "LSI80225/B"
76 #define STR_ID_DP83848VV "N83848"
77 #define STR_ID_DP83849 "N83849"
78
79 /****************************************************************************
80 * mii_init -- Initialize the MII for MII command without ethernet
81 * This function is a subset of eth_init
82 ****************************************************************************
83 */
84 void mii_reset(struct fec_info_s *info)
85 {
86 volatile fec_t *fecp = (fec_t *) (info->miibase);
87 int i;
88
89 fecp->ecr = FEC_ECR_RESET;
90 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
91 udelay(1);
92 }
93 if (i == FEC_RESET_DELAY) {
94 printf("FEC_RESET_DELAY timeout\n");
95 }
96 }
97
98 /* send command to phy using mii, wait for result */
99 uint mii_send(uint mii_cmd)
100 {
101 struct fec_info_s *info;
102 struct eth_device *dev;
103 volatile fec_t *ep;
104 uint mii_reply;
105 int j = 0;
106
107 /* retrieve from register structure */
108 dev = eth_get_dev();
109 info = dev->priv;
110
111 ep = (fec_t *) info->miibase;
112
113 ep->mmfr = mii_cmd; /* command to phy */
114
115 /* wait for mii complete */
116 while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
117 udelay(1);
118 j++;
119 }
120 if (j >= MCFFEC_TOUT_LOOP) {
121 printf("MII not complete\n");
122 return -1;
123 }
124
125 mii_reply = ep->mmfr; /* result from phy */
126 ep->eir = FEC_EIR_MII; /* clear MII complete */
127 #ifdef ET_DEBUG
128 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
129 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
130 #endif
131
132 return (mii_reply & 0xffff); /* data read from phy */
133 }
134 #endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
135
136 #if defined(CONFIG_SYS_DISCOVER_PHY)
137 int mii_discover_phy(struct eth_device *dev)
138 {
139 #define MAX_PHY_PASSES 11
140 struct fec_info_s *info = dev->priv;
141 int phyaddr, pass;
142 uint phyno, phytype;
143
144 if (info->phyname_init)
145 return info->phy_addr;
146
147 phyaddr = -1; /* didn't find a PHY yet */
148 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
149 if (pass > 1) {
150 /* PHY may need more time to recover from reset.
151 * The LXT970 needs 50ms typical, no maximum is
152 * specified, so wait 10ms before try again.
153 * With 11 passes this gives it 100ms to wake up.
154 */
155 udelay(10000); /* wait 10ms */
156 }
157
158 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
159
160 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
161 #ifdef ET_DEBUG
162 printf("PHY type 0x%x pass %d type\n", phytype, pass);
163 #endif
164 if (phytype != 0xffff) {
165 phyaddr = phyno;
166 phytype <<= 16;
167 phytype |=
168 mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
169
170 switch (phytype & 0xffffffff) {
171 case PHY_ID_AMD79C874VC:
172 strcpy(info->phy_name,
173 STR_ID_AMD79C874VC);
174 info->phyname_init = 1;
175 break;
176 default:
177 strcpy(info->phy_name, "unknown");
178 info->phyname_init = 1;
179 break;
180 }
181
182 #ifdef ET_DEBUG
183 printf("PHY @ 0x%x pass %d type ", phyno, pass);
184 switch (phytype & 0xffffffff) {
185 case PHY_ID_AMD79C874VC:
186 printf(STR_ID_AMD79C874VC);
187 break;
188 default:
189 printf("0x%08x\n", phytype);
190 break;
191 }
192 #endif
193 }
194 }
195 }
196 if (phyaddr < 0)
197 printf("No PHY device found.\n");
198
199 return phyaddr;
200 }
201 #endif /* CONFIG_SYS_DISCOVER_PHY */
202
203 void mii_init(void) __attribute__((weak,alias("__mii_init")));
204
205 void __mii_init(void)
206 {
207 volatile fec_t *fecp;
208 struct fec_info_s *info;
209 struct eth_device *dev;
210 int miispd = 0, i = 0;
211 u16 autoneg = 0;
212
213 /* retrieve from register structure */
214 dev = eth_get_dev();
215 info = dev->priv;
216
217 fecp = (fec_t *) info->miibase;
218
219 fecpin_setclear(dev, 1);
220
221 mii_reset(info);
222
223 /* We use strictly polling mode only */
224 fecp->eimr = 0;
225
226 /* Clear any pending interrupt */
227 fecp->eir = 0xffffffff;
228
229 /* Set MII speed */
230 miispd = (gd->bus_clk / 1000000) / 5;
231 fecp->mscr = miispd << 1;
232
233 info->phy_addr = mii_discover_phy(dev);
234
235 #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
236 while (i < MCFFEC_TOUT_LOOP) {
237 autoneg = 0;
238 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
239 i++;
240
241 if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
242 break;
243
244 udelay(500);
245 }
246 if (i >= MCFFEC_TOUT_LOOP) {
247 printf("Auto Negotiation not complete\n");
248 }
249
250 /* adapt to the half/full speed settings */
251 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
252 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
253 }
254
255 /*****************************************************************************
256 * Read and write a MII PHY register, routines used by MII Utilities
257 *
258 * FIXME: These routines are expected to return 0 on success, but mii_send
259 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
260 * no PHY connected...
261 * For now always return 0.
262 * FIXME: These routines only work after calling eth_init() at least once!
263 * Otherwise they hang in mii_send() !!! Sorry!
264 *****************************************************************************/
265
266 int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
267 unsigned short *value)
268 {
269 short rdreg; /* register working value */
270
271 #ifdef MII_DEBUG
272 printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
273 #endif
274 rdreg = mii_send(mk_mii_read(addr, reg));
275
276 *value = rdreg;
277
278 #ifdef MII_DEBUG
279 printf("0x%04x\n", *value);
280 #endif
281
282 return 0;
283 }
284
285 int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
286 unsigned short value)
287 {
288 short rdreg; /* register working value */
289
290 #ifdef MII_DEBUG
291 printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
292 #endif
293
294 rdreg = mii_send(mk_mii_write(addr, reg, value));
295
296 #ifdef MII_DEBUG
297 printf("0x%04x\n", value);
298 #endif
299
300 return 0;
301 }
302
303 #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */