board/freescale/m5282evb/m5282evb.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/immap.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int checkboard (void)
  30 {
  31         puts ("Board: Freescale M5282EVB Evaluation Board\n");
  32         return 0;
  33 }
  34
  35 phys_size_t initdram (int board_type)
  36 {
  37         u32 dramsize, i, dramclk;
  38
  39         dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  40         for (i = 0x13; i < 0x20; i++) {
  41                 if (dramsize == (1 << i))
  42                         break;
  43         }
  44         i--;
  45
  46         if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
  47         {
  48                 dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
  49
  50                 /* Initialize DRAM Control Register: DCR */
  51                 MCFSDRAMC_DCR = (0
  52                         | MCFSDRAMC_DCR_RTIM_6
  53                         | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
  54                 asm("nop");
  55
  56                 /* Initialize DACR0 */
  57                 MCFSDRAMC_DACR0 = (0
  58                         | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
  59                         | MCFSDRAMC_DACR_CASL(1)
  60                         | MCFSDRAMC_DACR_CBM(3)
  61                         | MCFSDRAMC_DACR_PS_32);
  62                 asm("nop");
  63
  64                 /* Initialize DMR0 */
  65                 MCFSDRAMC_DMR0 = (0
  66                         | ((dramsize - 1) & 0xFFFC0000)
  67                         | MCFSDRAMC_DMR_V);
  68                 asm("nop");
  69
  70                 /* Set IP (bit 3) in DACR */
  71                 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
  72                 asm("nop");
  73
  74                 /* Wait 30ns to allow banks to precharge */
  75                 for (i = 0; i < 5; i++) {
  76                         asm ("nop");
  77                 }
  78
  79                 /* Write to this block to initiate precharge */
  80                 *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
  81                 asm("nop");
  82
  83                 /* Set RE (bit 15) in DACR */
  84                 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
  85                 asm("nop");
  86
  87                 /* Wait for at least 8 auto refresh cycles to occur */
  88                 for (i = 0; i < 2000; i++) {
  89                         asm(" nop");
  90                 }
  91
  92                 /* Finish the configuration by issuing the IMRS. */
  93                 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
  94                 asm("nop");
  95
  96                 /* Write to the SDRAM Mode Register */
  97                 *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
  98         }
  99         return dramsize;
 100 }