]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/freescale/m54455evb/mii.c
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / freescale / m54455evb / mii.c
1 /*
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <asm/fec.h>
26 #include <asm/immap.h>
27
28 #include <config.h>
29 #include <net.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
34 #undef MII_DEBUG
35 #undef ET_DEBUG
36
37 int fecpin_setclear(struct eth_device *dev, int setclear)
38 {
39 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
40 struct fec_info_s *info = (struct fec_info_s *)dev->priv;
41
42 if (setclear) {
43 gpio->par_feci2c |=
44 (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
45
46 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
47 gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
48 else
49 gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
50 } else {
51 gpio->par_feci2c &=
52 ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
53
54 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
55 gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
56 else
57 gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
58 }
59 return 0;
60 }
61
62 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
63 #include <miiphy.h>
64
65 /* Make MII read/write commands for the FEC. */
66 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
67
68 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
69
70 /* PHY identification */
71 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
72 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
73 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
74 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
75 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
76 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
77 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
78 #define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
79 #define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
80
81 #define STR_ID_LXT970 "LXT970"
82 #define STR_ID_LXT971 "LXT971"
83 #define STR_ID_82555 "Intel82555"
84 #define STR_ID_QS6612 "QS6612"
85 #define STR_ID_AMD79C784 "AMD79C784"
86 #define STR_ID_LSI80225 "LSI80225"
87 #define STR_ID_LSI80225B "LSI80225/B"
88 #define STR_ID_DP83848VV "N83848"
89 #define STR_ID_DP83849 "N83849"
90
91 /****************************************************************************
92 * mii_init -- Initialize the MII for MII command without ethernet
93 * This function is a subset of eth_init
94 ****************************************************************************
95 */
96 void mii_reset(struct fec_info_s *info)
97 {
98 volatile fec_t *fecp = (fec_t *) (info->miibase);
99 struct eth_device *dev;
100 int i, miispd;
101 u16 rst = 0;
102
103 dev = eth_get_dev();
104
105 miispd = (gd->bus_clk / 1000000) / 5;
106 fecp->mscr = miispd << 1;
107
108 miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
109 for (i = 0; i < FEC_RESET_DELAY; ++i) {
110 udelay(500);
111 miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
112 if ((rst & PHY_BMCR_RESET) == 0)
113 break;
114 }
115 if (i == FEC_RESET_DELAY)
116 printf("Mii reset timeout %d\n", i);
117 }
118
119 /* send command to phy using mii, wait for result */
120 uint mii_send(uint mii_cmd)
121 {
122 struct fec_info_s *info;
123 struct eth_device *dev;
124 volatile fec_t *ep;
125 uint mii_reply;
126 int j = 0;
127
128 /* retrieve from register structure */
129 dev = eth_get_dev();
130 info = dev->priv;
131
132 ep = (fec_t *) info->miibase;
133
134 ep->mmfr = mii_cmd; /* command to phy */
135
136 /* wait for mii complete */
137 while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
138 udelay(1);
139 j++;
140 }
141 if (j >= MCFFEC_TOUT_LOOP) {
142 printf("MII not complete\n");
143 return -1;
144 }
145
146 mii_reply = ep->mmfr; /* result from phy */
147 ep->eir = FEC_EIR_MII; /* clear MII complete */
148 #ifdef ET_DEBUG
149 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
150 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
151 #endif
152
153 return (mii_reply & 0xffff); /* data read from phy */
154 }
155 #endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
156
157 #if defined(CONFIG_SYS_DISCOVER_PHY)
158 int mii_discover_phy(struct eth_device *dev)
159 {
160 #define MAX_PHY_PASSES 11
161 struct fec_info_s *info = dev->priv;
162 int phyaddr, pass;
163 uint phyno, phytype;
164
165 if (info->phyname_init)
166 return info->phy_addr;
167
168 phyaddr = -1; /* didn't find a PHY yet */
169 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
170 if (pass > 1) {
171 /* PHY may need more time to recover from reset.
172 * The LXT970 needs 50ms typical, no maximum is
173 * specified, so wait 10ms before try again.
174 * With 11 passes this gives it 100ms to wake up.
175 */
176 udelay(10000); /* wait 10ms */
177 }
178
179 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
180
181 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
182 #ifdef ET_DEBUG
183 printf("PHY type 0x%x pass %d type\n", phytype, pass);
184 #endif
185 if (phytype != 0xffff) {
186 phyaddr = phyno;
187 phytype <<= 16;
188 phytype |=
189 mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
190
191 switch (phytype & 0xffffffff) {
192 case PHY_ID_DP83848VV:
193 strcpy(info->phy_name,
194 STR_ID_DP83848VV);
195 info->phyname_init = 1;
196 break;
197 default:
198 strcpy(info->phy_name, "unknown");
199 info->phyname_init = 1;
200 break;
201 }
202
203 #ifdef ET_DEBUG
204 printf("PHY @ 0x%x pass %d type ", phyno, pass);
205 switch (phytype & 0xffffffff) {
206 case PHY_ID_DP83848VV:
207 printf(STR_ID_DP83848VV);
208 break;
209 default:
210 printf("0x%08x\n", phytype);
211 break;
212 }
213 #endif
214 }
215 }
216 }
217 if (phyaddr < 0)
218 printf("No PHY device found.\n");
219
220 return phyaddr;
221 }
222 #endif /* CONFIG_SYS_DISCOVER_PHY */
223
224 void mii_init(void) __attribute__((weak,alias("__mii_init")));
225
226 void __mii_init(void)
227 {
228 volatile fec_t *fecp;
229 struct fec_info_s *info;
230 struct eth_device *dev;
231 int miispd = 0, i = 0;
232 u16 autoneg = 0;
233
234 /* retrieve from register structure */
235 dev = eth_get_dev();
236 info = dev->priv;
237
238 fecp = (fec_t *) info->miibase;
239
240 fecpin_setclear(dev, 1);
241
242 mii_reset(info);
243
244 /* We use strictly polling mode only */
245 fecp->eimr = 0;
246
247 /* Clear any pending interrupt */
248 fecp->eir = 0xffffffff;
249
250 /* Set MII speed */
251 miispd = (gd->bus_clk / 1000000) / 5;
252 fecp->mscr = miispd << 1;
253
254 info->phy_addr = mii_discover_phy(dev);
255
256 #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
257 while (i < MCFFEC_TOUT_LOOP) {
258 autoneg = 0;
259 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
260 i++;
261
262 if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
263 break;
264
265 udelay(500);
266 }
267 if (i >= MCFFEC_TOUT_LOOP) {
268 printf("Auto Negotiation not complete\n");
269 }
270
271 /* adapt to the half/full speed settings */
272 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
273 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
274 }
275
276 /*****************************************************************************
277 * Read and write a MII PHY register, routines used by MII Utilities
278 *
279 * FIXME: These routines are expected to return 0 on success, but mii_send
280 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
281 * no PHY connected...
282 * For now always return 0.
283 * FIXME: These routines only work after calling eth_init() at least once!
284 * Otherwise they hang in mii_send() !!! Sorry!
285 *****************************************************************************/
286
287 int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
288 unsigned short *value)
289 {
290 short rdreg; /* register working value */
291
292 #ifdef MII_DEBUG
293 printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
294 #endif
295 rdreg = mii_send(mk_mii_read(addr, reg));
296
297 *value = rdreg;
298
299 #ifdef MII_DEBUG
300 printf("0x%04x\n", *value);
301 #endif
302
303 return 0;
304 }
305
306 int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
307 unsigned short value)
308 {
309 short rdreg; /* register working value */
310
311 #ifdef MII_DEBUG
312 printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
313 #endif
314
315 rdreg = mii_send(mk_mii_write(addr, reg, value));
316
317 #ifdef MII_DEBUG
318 printf("0x%04x\n", value);
319 #endif
320
321 return 0;
322 }
323
324 #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */