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git.ipfire.org Git - people/ms/u-boot.git/blob - board/freescale/m548xevb/mii.c
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/immap.h>
30 #include <asm/fsl_mcdmafec.h>
32 DECLARE_GLOBAL_DATA_PTR
;
34 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
38 int fecpin_setclear(struct eth_device
*dev
, int setclear
)
40 volatile gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
41 struct fec_info_dma
*info
= (struct fec_info_dma
*)dev
->priv
;
44 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
)
45 gpio
->par_feci2cirq
|= 0xF000;
47 gpio
->par_feci2cirq
|= 0x0FC0;
49 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
)
50 gpio
->par_feci2cirq
&= 0x0FFF;
52 gpio
->par_feci2cirq
&= 0xF03F;
57 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
60 /* Make MII read/write commands for the FEC. */
61 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
63 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
65 /* PHY identification */
66 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
67 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
68 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
69 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
70 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
71 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
72 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
73 #define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
74 #define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
75 #define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
77 #define STR_ID_LXT970 "LXT970"
78 #define STR_ID_LXT971 "LXT971"
79 #define STR_ID_82555 "Intel82555"
80 #define STR_ID_QS6612 "QS6612"
81 #define STR_ID_AMD79C784 "AMD79C784"
82 #define STR_ID_LSI80225 "LSI80225"
83 #define STR_ID_LSI80225B "LSI80225/B"
84 #define STR_ID_DP83848VV "N83848"
85 #define STR_ID_DP83849 "N83849"
86 #define STR_ID_BCM5222 "BCM5222"
88 /****************************************************************************
89 * mii_init -- Initialize the MII for MII command without ethernet
90 * This function is a subset of eth_init
91 ****************************************************************************
93 void mii_reset(struct fec_info_dma
*info
)
95 volatile fecdma_t
*fecp
= (fecdma_t
*) (info
->miibase
);
98 fecp
->ecr
= FEC_ECR_RESET
;
99 for (i
= 0; (fecp
->ecr
& FEC_ECR_RESET
) && (i
< FEC_RESET_DELAY
); ++i
) {
102 if (i
== FEC_RESET_DELAY
) {
103 printf("FEC_RESET_DELAY timeout\n");
107 /* send command to phy using mii, wait for result */
108 uint
mii_send(uint mii_cmd
)
110 struct fec_info_dma
*info
;
111 struct eth_device
*dev
;
112 volatile fecdma_t
*ep
;
116 /* retrieve from register structure */
120 ep
= (fecdma_t
*) info
->miibase
;
122 ep
->mmfr
= mii_cmd
; /* command to phy */
124 /* wait for mii complete */
125 while (!(ep
->eir
& FEC_EIR_MII
) && (j
< MCFFEC_TOUT_LOOP
)) {
129 if (j
>= MCFFEC_TOUT_LOOP
) {
130 printf("MII not complete\n");
134 mii_reply
= ep
->mmfr
; /* result from phy */
135 ep
->eir
= FEC_EIR_MII
; /* clear MII complete */
137 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
138 __FILE__
, __LINE__
, __FUNCTION__
, mii_cmd
, mii_reply
);
141 return (mii_reply
& 0xffff); /* data read from phy */
143 #endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
145 #if defined(CONFIG_SYS_DISCOVER_PHY)
146 int mii_discover_phy(struct eth_device
*dev
)
148 #define MAX_PHY_PASSES 11
149 struct fec_info_dma
*info
= dev
->priv
;
150 int phyaddr
, pass
, temp
;
153 if (info
->phyname_init
) {
154 return info
->phy_addr
;
157 phyaddr
= -1; /* didn't find a PHY yet */
158 for (pass
= 1; pass
<= MAX_PHY_PASSES
&& phyaddr
< 0; ++pass
) {
160 /* PHY may need more time to recover from reset.
161 * The LXT970 needs 50ms typical, no maximum is
162 * specified, so wait 10ms before try again.
163 * With 11 passes this gives it 100ms to wake up.
165 udelay(10000); /* wait 10ms */
169 if (info
->index
> 0) {
170 /* Some phy have multiple address, to solve the issue
171 where phyno keeps starting from 0, check the
172 previous phy address if both miibase are the same. */
173 if (info
->miibase
== (info
->next
)->miibase
) {
174 temp
= (info
->next
)->phy_addr
+ 1;
178 for (phyno
= temp
; phyno
< 32 && phyaddr
< 0; ++phyno
) {
180 phytype
= mii_send(mk_mii_read(phyno
, PHY_PHYIDR1
));
182 printf("PHY type 0x%x pass %d type\n", phytype
, pass
);
184 if (phytype
!= 0xffff) {
188 mii_send(mk_mii_read(phyno
, PHY_PHYIDR2
));
190 switch (phytype
& 0xffffffff) {
192 strcpy(info
->phy_name
, STR_ID_BCM5222
);
193 info
->phyname_init
= 1;
196 strcpy(info
->phy_name
, "unknown");
197 info
->phyname_init
= 1;
202 printf("PHY @ 0x%x pass %d type ", phyno
, pass
);
203 switch (phytype
& 0xffffffff) {
205 printf(STR_ID_BCM5222
);
208 printf("0x%08x\n", phytype
);
216 printf("No PHY device found.\n");
220 #endif /* CONFIG_SYS_DISCOVER_PHY */
222 void mii_init(void) __attribute__ ((weak
, alias("__mii_init")));
224 void __mii_init(void)
226 volatile fecdma_t
*fecp
;
227 struct fec_info_dma
*info
;
228 struct eth_device
*dev
;
229 int miispd
= 0, i
= 0;
232 /* retrieve from register structure */
236 fecp
= (fecdma_t
*) info
->miibase
;
238 fecpin_setclear(dev
, 1);
242 /* We use strictly polling mode only */
245 /* Clear any pending interrupt */
246 fecp
->eir
= 0xffffffff;
249 miispd
= (gd
->bus_clk
/ 1000000) / 5;
250 fecp
->mscr
= miispd
<< 1;
252 info
->phy_addr
= mii_discover_phy(dev
);
254 #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
255 while (i
< MCFFEC_TOUT_LOOP
) {
257 miiphy_read(dev
->name
, info
->phy_addr
, PHY_BMSR
, &autoneg
);
260 if ((autoneg
& AUTONEGLINK
) == AUTONEGLINK
)
265 if (i
>= MCFFEC_TOUT_LOOP
) {
266 printf("Auto Negotiation not complete\n");
269 /* adapt to the half/full speed settings */
270 info
->dup_spd
= miiphy_duplex(dev
->name
, info
->phy_addr
) << 16;
271 info
->dup_spd
|= miiphy_speed(dev
->name
, info
->phy_addr
);
274 /*****************************************************************************
275 * Read and write a MII PHY register, routines used by MII Utilities
277 * FIXME: These routines are expected to return 0 on success, but mii_send
278 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
279 * no PHY connected...
280 * For now always return 0.
281 * FIXME: These routines only work after calling eth_init() at least once!
282 * Otherwise they hang in mii_send() !!! Sorry!
283 *****************************************************************************/
285 int mcffec_miiphy_read(char *devname
, unsigned char addr
, unsigned char reg
,
286 unsigned short *value
)
288 short rdreg
; /* register working value */
291 printf("miiphy_read(0x%x) @ 0x%x = ", reg
, addr
);
293 rdreg
= mii_send(mk_mii_read(addr
, reg
));
298 printf("0x%04x\n", *value
);
304 int mcffec_miiphy_write(char *devname
, unsigned char addr
, unsigned char reg
,
305 unsigned short value
)
307 short rdreg
; /* register working value */
310 printf("miiphy_write(0x%x) @ 0x%x = ", reg
, addr
);
313 rdreg
= mii_send(mk_mii_write(addr
, reg
, value
));
316 printf("0x%04x\n", value
);
322 #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */