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mpc512x: MPC5121ADS: Add NAND support
[people/ms/u-boot.git] / board / freescale / mpc5121ads / mpc5121ads.c
1 /*
2 * (C) Copyright 2007-2009 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24 #include <common.h>
25 #include <asm/bitops.h>
26 #include <command.h>
27 #include <asm/io.h>
28 #include <asm/processor.h>
29 #include <fdt_support.h>
30 #ifdef CONFIG_MISC_INIT_R
31 #include <i2c.h>
32 #endif
33
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/nand.h>
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 extern int mpc5121_diu_init(void);
40 extern void ide_set_reset(int idereset);
41
42 /* Clocks in use */
43 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
44 CLOCK_SCCR1_DDR_EN | \
45 CLOCK_SCCR1_FEC_EN | \
46 CLOCK_SCCR1_LPC_EN | \
47 CLOCK_SCCR1_NFC_EN | \
48 CLOCK_SCCR1_PATA_EN | \
49 CLOCK_SCCR1_PCI_EN | \
50 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
51 CLOCK_SCCR1_PSCFIFO_EN | \
52 CLOCK_SCCR1_TPR_EN)
53
54 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
55 CLOCK_SCCR2_I2C_EN | \
56 CLOCK_SCCR2_MEM_EN | \
57 CLOCK_SCCR2_SPDIF_EN)
58
59 #define CSAW_START(start) ((start) & 0xFFFF0000)
60 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
61
62 long int fixed_sdram(void);
63 void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
64
65 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
66 extern int mpc5121_nfc_chip;
67
68 /* Control chips select signal on MPC5121ADS board */
69 void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
70 {
71 unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
72 u8 v;
73
74 v = in_8(csreg);
75 v |= 0x0F;
76
77 if (chip >= 0) {
78 __mpc5121_nfc_select_chip(mtd, 0);
79 v &= ~(1 << mpc5121_nfc_chip);
80 } else {
81 __mpc5121_nfc_select_chip(mtd, -1);
82 }
83
84 out_8(csreg, v);
85 }
86
87 int board_early_init_f (void)
88 {
89 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
90 u32 lpcaw, spridr;
91
92 /*
93 * Initialize Local Window for the CPLD registers access (CS2 selects
94 * the CPLD chip)
95 */
96 out_be32(&im->sysconf.lpcs2aw,
97 CSAW_START(CONFIG_SYS_CPLD_BASE) |
98 CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
99 );
100 out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
101
102 /*
103 * According to MPC5121e RM, configuring local access windows should
104 * be followed by a dummy read of the config register that was
105 * modified last and an isync
106 */
107 lpcaw = in_be32(&im->sysconf.lpcs6aw);
108 __asm__ __volatile__ ("isync");
109
110 /*
111 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
112 *
113 * Without this the flash identification routine fails, as it needs to issue
114 * write commands in order to establish the device ID.
115 */
116
117 #ifdef CONFIG_ADS5121_REV2
118 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
119 #else
120 if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
121 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
122 } else {
123 /* running from Backup flash */
124 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
125 }
126 #endif
127 /*
128 * Configure Flash Speed
129 */
130 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
131
132 spridr = in_be32(&im->sysconf.spridr);
133
134 if (SVR_MJREV (spridr) >= 2)
135 out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
136
137 /*
138 * Enable clocks
139 */
140 out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
141 out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
142 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
143 setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
144 #endif
145
146 return 0;
147 }
148
149 phys_size_t initdram (int board_type)
150 {
151 u32 msize = 0;
152
153 msize = fixed_sdram ();
154
155 return msize;
156 }
157
158 /*
159 * fixed sdram init -- the board doesn't use memory modules that have serial presence
160 * detect or similar mechanism for discovery of the DRAM settings
161 */
162 long int fixed_sdram (void)
163 {
164 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
165 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
166 u32 msize_log2 = __ilog2 (msize);
167 u32 i;
168
169 /* Initialize IO Control */
170 out_be32 (&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
171
172 /* Initialize DDR Local Window */
173 out_be32 (&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
174 out_be32 (&im->sysconf.ddrlaw.ar, msize_log2 - 1);
175
176 /*
177 * According to MPC5121e RM, configuring local access windows should
178 * be followed by a dummy read of the config register that was
179 * modified last and an isync
180 */
181 in_be32(&im->sysconf.ddrlaw.ar);
182 __asm__ __volatile__ ("isync");
183
184 /* Enable DDR */
185 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
186
187 /* Initialize DDR Priority Manager */
188 out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
189 out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
190 out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
191 out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
192 out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
193 out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
194 out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
195 out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
196 out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
197 out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
198 out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
199 out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
200 out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
201 out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
202 out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
203 out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
204 out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
205 out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
206 out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
207 out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
208 out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
209 out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
210 out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
211
212 /* Initialize MDDRC */
213 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
214 out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
215 out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
216 out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
217
218 /* Initialize DDR */
219 for (i = 0; i < 10; i++)
220 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
221
222 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
223 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
224 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
225 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
226 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
227 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
228 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
229 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
230 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
231 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
232 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
233 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
234 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
235 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
236 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
237 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
238 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
239 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
240 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
241 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
242 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
243
244 /* Start MDDRC */
245 out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
246 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
247
248 return msize;
249 }
250
251 int misc_init_r(void)
252 {
253 u8 tmp_val;
254
255 /* Using this for DIU init before the driver in linux takes over
256 * Enable the TFP410 Encoder (I2C address 0x38)
257 */
258
259 i2c_set_bus_num(2);
260 tmp_val = 0xBF;
261 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
262 /* Verify if enabled */
263 tmp_val = 0;
264 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
265 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
266
267 tmp_val = 0x10;
268 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
269 /* Verify if enabled */
270 tmp_val = 0;
271 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
272 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
273
274 #ifdef CONFIG_FSL_DIU_FB
275 # if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
276 mpc5121_diu_init();
277 # endif
278 #endif
279 return 0;
280 }
281
282 static iopin_t ioregs_init[] = {
283 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
284 {
285 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
286 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
287 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
288 },
289 /* Set highest Slew on 9 PATA pins */
290 {
291 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
292 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
293 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
294 },
295 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
296 {
297 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
298 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
299 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
300 },
301 /* FUNC1=SPDIF_TXCLK */
302 {
303 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
304 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
305 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
306 },
307 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
308 {
309 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
310 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
311 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
312 },
313 /* FUNC2=DIU CLK */
314 {
315 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
316 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
317 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
318 },
319 /* FUNC2=DIU_HSYNC */
320 {
321 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
322 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
323 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
324 },
325 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
326 {
327 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
328 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
329 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
330 }
331 };
332
333 static iopin_t rev2_silicon_pci_ioregs_init[] = {
334 /* FUNC0=PCI Sets next 54 to PCI pads */
335 {
336 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
337 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
338 }
339 };
340
341 int checkboard (void)
342 {
343 ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
344 uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
345 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
346 u32 spridr = in_be32(&im->sysconf.spridr);
347
348 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
349 brd_rev, cpld_rev);
350
351 /* initialize function mux & slew rate IO inter alia on IO Pins */
352 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
353
354 if (SVR_MJREV (spridr) >= 2)
355 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
356
357 return 0;
358 }
359
360 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
361 void ft_board_setup(void *blob, bd_t *bd)
362 {
363 ft_cpu_setup(blob, bd);
364 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
365 }
366 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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