2 * (C) Copyright 2007-2009 DENX Software Engineering
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/bitops.h>
11 #include <asm/processor.h>
12 #include <asm/mpc512x.h>
13 #include <fdt_support.h>
14 #ifdef CONFIG_MISC_INIT_R
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
22 DECLARE_GLOBAL_DATA_PTR
;
24 void __mpc5121_nfc_select_chip(struct mtd_info
*mtd
, int chip
);
26 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
27 extern int mpc5121_nfc_chip
;
29 /* Control chips select signal on MPC5121ADS board */
30 void mpc5121_nfc_select_chip(struct mtd_info
*mtd
, int chip
)
32 unsigned char *csreg
= (u8
*)CONFIG_SYS_CPLD_BASE
+ 0x09;
39 __mpc5121_nfc_select_chip(mtd
, 0);
40 v
&= ~(1 << mpc5121_nfc_chip
);
42 __mpc5121_nfc_select_chip(mtd
, -1);
48 int board_early_init_f(void)
51 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
53 * Without this the flash identification routine fails, as it needs to issue
54 * write commands in order to establish the device ID.
57 #ifdef CONFIG_MPC5121ADS_REV2
58 out_8((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08), 0xC1);
60 if (in_8((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08)) & 0x04) {
61 out_8((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08), 0xC1);
63 /* running from Backup flash */
64 out_8((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08), 0x32);
72 ushort brd_rev
= *(vu_short
*)(CONFIG_SYS_CPLD_BASE
+ 0x00);
74 u32 brddate
, macchk
, ismicron
;
77 * MAC address has serial number with date of manufacture
78 * Boards made before Nov-08 #1180 use Micron memory;
79 * 001e59 is the STx vendor #
80 * Default is Elpida since it works for both but is slightly slower
83 if (brd_rev
>= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr
)) {
84 brddate
= (macaddr
[3] << 16) + (macaddr
[4] << 8) + macaddr
[5];
85 macchk
= (macaddr
[0] << 16) + (macaddr
[1] << 8) + macaddr
[2];
86 debug("brddate = %d\n\t", brddate
);
88 if (macchk
== 0x001e59 && brddate
<= 8111180)
90 } else if (brd_rev
< 0x400) {
93 debug("Using %s Memory settings\n\t",
94 ismicron
? "Micron" : "Elpida");
98 phys_size_t
initdram(int board_type
)
102 * Elpida MDDRC and initialization settings are an alternative
103 * to the Default Micron ones for all but the earliest Rev 4 boards
105 ddr512x_config_t elpida_mddrc_config
= {
106 .ddr_sys_config
= CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA
,
107 .ddr_time_config0
= CONFIG_SYS_MDDRC_TIME_CFG0
,
108 .ddr_time_config1
= CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA
,
109 .ddr_time_config2
= CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA
,
112 u32 elpida_init_sequence
[] = {
113 CONFIG_SYS_DDRCMD_NOP
,
114 CONFIG_SYS_DDRCMD_NOP
,
115 CONFIG_SYS_DDRCMD_NOP
,
116 CONFIG_SYS_DDRCMD_NOP
,
117 CONFIG_SYS_DDRCMD_NOP
,
118 CONFIG_SYS_DDRCMD_NOP
,
119 CONFIG_SYS_DDRCMD_NOP
,
120 CONFIG_SYS_DDRCMD_NOP
,
121 CONFIG_SYS_DDRCMD_NOP
,
122 CONFIG_SYS_DDRCMD_NOP
,
123 CONFIG_SYS_DDRCMD_PCHG_ALL
,
124 CONFIG_SYS_DDRCMD_NOP
,
125 CONFIG_SYS_DDRCMD_RFSH
,
126 CONFIG_SYS_DDRCMD_NOP
,
127 CONFIG_SYS_DDRCMD_RFSH
,
128 CONFIG_SYS_DDRCMD_NOP
,
129 CONFIG_SYS_DDRCMD_EM2
,
130 CONFIG_SYS_DDRCMD_EM3
,
131 CONFIG_SYS_DDRCMD_EN_DLL
,
132 CONFIG_SYS_ELPIDA_RES_DLL
,
133 CONFIG_SYS_DDRCMD_PCHG_ALL
,
134 CONFIG_SYS_DDRCMD_RFSH
,
135 CONFIG_SYS_DDRCMD_RFSH
,
136 CONFIG_SYS_DDRCMD_RFSH
,
137 CONFIG_SYS_ELPIDA_INIT_DEV_OP
,
138 CONFIG_SYS_DDRCMD_NOP
,
139 CONFIG_SYS_DDRCMD_NOP
,
140 CONFIG_SYS_DDRCMD_NOP
,
141 CONFIG_SYS_DDRCMD_NOP
,
142 CONFIG_SYS_DDRCMD_NOP
,
143 CONFIG_SYS_DDRCMD_NOP
,
144 CONFIG_SYS_DDRCMD_NOP
,
145 CONFIG_SYS_DDRCMD_NOP
,
146 CONFIG_SYS_DDRCMD_NOP
,
147 CONFIG_SYS_DDRCMD_NOP
,
148 CONFIG_SYS_DDRCMD_OCD_DEFAULT
,
149 CONFIG_SYS_ELPIDA_OCD_EXIT
,
150 CONFIG_SYS_DDRCMD_NOP
,
151 CONFIG_SYS_DDRCMD_NOP
,
152 CONFIG_SYS_DDRCMD_NOP
,
153 CONFIG_SYS_DDRCMD_NOP
,
154 CONFIG_SYS_DDRCMD_NOP
,
155 CONFIG_SYS_DDRCMD_NOP
,
156 CONFIG_SYS_DDRCMD_NOP
,
157 CONFIG_SYS_DDRCMD_NOP
,
158 CONFIG_SYS_DDRCMD_NOP
,
159 CONFIG_SYS_DDRCMD_NOP
163 msize
= fixed_sdram(NULL
, NULL
, 0);
165 msize
= fixed_sdram(&elpida_mddrc_config
,
166 elpida_init_sequence
,
167 sizeof(elpida_init_sequence
)/sizeof(u32
));
173 int misc_init_r(void)
177 /* Using this for DIU init before the driver in linux takes over
178 * Enable the TFP410 Encoder (I2C address 0x38)
183 i2c_write(0x38, 0x08, 1, &tmp_val
, sizeof(tmp_val
));
184 /* Verify if enabled */
186 i2c_read(0x38, 0x08, 1, &tmp_val
, sizeof(tmp_val
));
187 debug("DVI Encoder Read: 0x%02x\n", tmp_val
);
190 i2c_write(0x38, 0x0A, 1, &tmp_val
, sizeof(tmp_val
));
191 /* Verify if enabled */
193 i2c_read(0x38, 0x0A, 1, &tmp_val
, sizeof(tmp_val
));
194 debug("DVI Encoder Read: 0x%02x\n", tmp_val
);
199 static iopin_t ioregs_init
[] = {
200 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
202 offsetof(struct ioctrl512x
, io_control_spdif_txclk
), 3, 0,
203 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
204 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
206 /* Set highest Slew on 9 PATA pins */
208 offsetof(struct ioctrl512x
, io_control_pata_ce1
), 9, 1,
209 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
210 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
212 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
214 offsetof(struct ioctrl512x
, io_control_psc0_0
), 15, 0,
215 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
216 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
218 /* FUNC1=SPDIF_TXCLK */
220 offsetof(struct ioctrl512x
, io_control_lpc_cs1
), 1, 0,
221 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
222 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
224 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
226 offsetof(struct ioctrl512x
, io_control_i2c1_scl
), 2, 0,
227 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
228 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
232 offsetof(struct ioctrl512x
, io_control_psc6_0
), 1, 0,
233 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
234 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
236 /* FUNC2=DIU_HSYNC */
238 offsetof(struct ioctrl512x
, io_control_psc6_1
), 1, 0,
239 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
240 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
242 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
244 offsetof(struct ioctrl512x
, io_control_psc6_4
), 26, 0,
245 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
246 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
250 static iopin_t rev2_silicon_pci_ioregs_init
[] = {
251 /* FUNC0=PCI Sets next 54 to PCI pads */
253 offsetof(struct ioctrl512x
, io_control_pci_ad31
), 54, 0,
254 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
258 int checkboard (void)
260 ushort brd_rev
= *(vu_short
*) (CONFIG_SYS_CPLD_BASE
+ 0x00);
261 uchar cpld_rev
= *(vu_char
*) (CONFIG_SYS_CPLD_BASE
+ 0x02);
262 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
263 u32 spridr
= in_be32(&im
->sysconf
.spridr
);
265 printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
268 /* initialize function mux & slew rate IO inter alia on IO Pins */
269 iopin_initialize(ioregs_init
, ARRAY_SIZE(ioregs_init
));
271 if (SVR_MJREV (spridr
) >= 2)
272 iopin_initialize(rev2_silicon_pci_ioregs_init
, 1);
277 #ifdef CONFIG_OF_BOARD_SETUP
278 int ft_board_setup(void *blob
, bd_t
*bd
)
280 ft_cpu_setup(blob
, bd
);
284 #endif /* CONFIG_OF_BOARD_SETUP */