2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
20 #if defined(CONFIG_PCI)
23 #if defined(CONFIG_SPD_EEPROM)
24 #include <spd_sdram.h>
28 #if defined(CONFIG_OF_FLAT_TREE)
30 #elif defined(CONFIG_OF_LIBFDT)
33 #if defined(CONFIG_PQ_MDS_PIB)
34 #include "../common/pq-mds-pib.h"
37 const qe_iop_conf_t qe_iop_conf_tab
[] = {
39 {0, 3, 1, 0, 1}, /* TxD0 */
40 {0, 4, 1, 0, 1}, /* TxD1 */
41 {0, 5, 1, 0, 1}, /* TxD2 */
42 {0, 6, 1, 0, 1}, /* TxD3 */
43 {1, 6, 1, 0, 3}, /* TxD4 */
44 {1, 7, 1, 0, 1}, /* TxD5 */
45 {1, 9, 1, 0, 2}, /* TxD6 */
46 {1, 10, 1, 0, 2}, /* TxD7 */
47 {0, 9, 2, 0, 1}, /* RxD0 */
48 {0, 10, 2, 0, 1}, /* RxD1 */
49 {0, 11, 2, 0, 1}, /* RxD2 */
50 {0, 12, 2, 0, 1}, /* RxD3 */
51 {0, 13, 2, 0, 1}, /* RxD4 */
52 {1, 1, 2, 0, 2}, /* RxD5 */
53 {1, 0, 2, 0, 2}, /* RxD6 */
54 {1, 4, 2, 0, 2}, /* RxD7 */
55 {0, 7, 1, 0, 1}, /* TX_EN */
56 {0, 8, 1, 0, 1}, /* TX_ER */
57 {0, 15, 2, 0, 1}, /* RX_DV */
58 {0, 16, 2, 0, 1}, /* RX_ER */
59 {0, 0, 2, 0, 1}, /* RX_CLK */
60 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
61 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
63 {0, 17, 1, 0, 1}, /* TxD0 */
64 {0, 18, 1, 0, 1}, /* TxD1 */
65 {0, 19, 1, 0, 1}, /* TxD2 */
66 {0, 20, 1, 0, 1}, /* TxD3 */
67 {1, 2, 1, 0, 1}, /* TxD4 */
68 {1, 3, 1, 0, 2}, /* TxD5 */
69 {1, 5, 1, 0, 3}, /* TxD6 */
70 {1, 8, 1, 0, 3}, /* TxD7 */
71 {0, 23, 2, 0, 1}, /* RxD0 */
72 {0, 24, 2, 0, 1}, /* RxD1 */
73 {0, 25, 2, 0, 1}, /* RxD2 */
74 {0, 26, 2, 0, 1}, /* RxD3 */
75 {0, 27, 2, 0, 1}, /* RxD4 */
76 {1, 12, 2, 0, 2}, /* RxD5 */
77 {1, 13, 2, 0, 3}, /* RxD6 */
78 {1, 11, 2, 0, 2}, /* RxD7 */
79 {0, 21, 1, 0, 1}, /* TX_EN */
80 {0, 22, 1, 0, 1}, /* TX_ER */
81 {0, 29, 2, 0, 1}, /* RX_DV */
82 {0, 30, 2, 0, 1}, /* RX_ER */
83 {0, 31, 2, 0, 1}, /* RX_CLK */
84 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
85 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
87 {0, 1, 3, 0, 2}, /* MDIO */
88 {0, 2, 1, 0, 1}, /* MDC */
90 {5, 0, 1, 0, 2}, /* UART2_SOUT */
91 {5, 1, 2, 0, 3}, /* UART2_CTS */
92 {5, 2, 1, 0, 1}, /* UART2_RTS */
93 {5, 3, 2, 0, 2}, /* UART2_SIN */
95 {0, 0, 0, 0, QE_IOP_TAB_END
}, /* END of table */
98 int board_early_init_f(void)
101 u8
*bcsr
= (u8
*)CFG_BCSR
;
102 const immap_t
*immr
= (immap_t
*)CFG_IMMR
;
104 /* Enable flash write */
107 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
108 if (immr
->sysconf
.spridr
== SPR_8360_REV20
||
109 immr
->sysconf
.spridr
== SPR_8360E_REV20
||
110 immr
->sysconf
.spridr
== SPR_8360_REV21
||
111 immr
->sysconf
.spridr
== SPR_8360E_REV21
)
114 /* Enable second UART */
120 int board_early_init_r(void)
122 #ifdef CONFIG_PQ_MDS_PIB
128 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
129 extern void ddr_enable_ecc(unsigned int dram_size
);
131 int fixed_sdram(void);
132 void sdram_init(void);
134 long int initdram(int board_type
)
136 volatile immap_t
*im
= (immap_t
*) CFG_IMMR
;
139 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
142 /* DDR SDRAM - Main SODIMM */
143 im
->sysconf
.ddrlaw
[0].bar
= CFG_DDR_BASE
& LAWBAR_BAR
;
144 #if defined(CONFIG_SPD_EEPROM)
147 msize
= fixed_sdram();
150 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
152 * Initialize DDR ECC byte
154 ddr_enable_ecc(msize
* 1024 * 1024);
157 * Initialize SDRAM if it is on local bus.
161 /* return total bus SDRAM size(bytes) -- DDR */
162 return (msize
* 1024 * 1024);
165 #if !defined(CONFIG_SPD_EEPROM)
166 /*************************************************************************
167 * fixed sdram init -- doesn't use serial presence detect.
168 ************************************************************************/
169 int fixed_sdram(void)
171 volatile immap_t
*im
= (immap_t
*) CFG_IMMR
;
176 msize
= CFG_DDR_SIZE
;
177 for (ddr_size
= msize
<< 20, ddr_size_log2
= 0;
178 (ddr_size
> 1); ddr_size
= ddr_size
>> 1, ddr_size_log2
++) {
183 im
->sysconf
.ddrlaw
[0].ar
=
184 LAWAR_EN
| ((ddr_size_log2
- 1) & LAWAR_SIZE
);
185 #if (CFG_DDR_SIZE != 256)
186 #warning Currenly any ddr size other than 256 is not supported
189 im
->ddr
.csbnds
[0].csbnds
= CFG_DDR_CS0_BNDS
;
190 im
->ddr
.cs_config
[0] = CFG_DDR_CS0_CONFIG
;
191 im
->ddr
.timing_cfg_0
= CFG_DDR_TIMING_0
;
192 im
->ddr
.timing_cfg_1
= CFG_DDR_TIMING_1
;
193 im
->ddr
.timing_cfg_2
= CFG_DDR_TIMING_2
;
194 im
->ddr
.timing_cfg_3
= CFG_DDR_TIMING_3
;
195 im
->ddr
.sdram_cfg
= CFG_DDR_SDRAM_CFG
;
196 im
->ddr
.sdram_cfg2
= CFG_DDR_SDRAM_CFG2
;
197 im
->ddr
.sdram_mode
= CFG_DDR_MODE
;
198 im
->ddr
.sdram_mode2
= CFG_DDR_MODE2
;
199 im
->ddr
.sdram_interval
= CFG_DDR_INTERVAL
;
200 im
->ddr
.sdram_clk_cntl
= CFG_DDR_CLK_CNTL
;
202 im
->ddr
.csbnds
[0].csbnds
= 0x00000007;
203 im
->ddr
.csbnds
[1].csbnds
= 0x0008000f;
205 im
->ddr
.cs_config
[0] = CFG_DDR_CONFIG
;
206 im
->ddr
.cs_config
[1] = CFG_DDR_CONFIG
;
208 im
->ddr
.timing_cfg_1
= CFG_DDR_TIMING_1
;
209 im
->ddr
.timing_cfg_2
= CFG_DDR_TIMING_2
;
210 im
->ddr
.sdram_cfg
= CFG_DDR_CONTROL
;
212 im
->ddr
.sdram_mode
= CFG_DDR_MODE
;
213 im
->ddr
.sdram_interval
= CFG_DDR_INTERVAL
;
216 im
->ddr
.sdram_cfg
|= SDRAM_CFG_MEM_EN
;
220 #endif /*!CFG_SPD_EEPROM */
224 puts("Board: Freescale MPC8360EMDS\n");
229 * if MPC8360EMDS is soldered with SDRAM
231 #if defined(CFG_BR2_PRELIM) \
232 && defined(CFG_OR2_PRELIM) \
233 && defined(CFG_LBLAWBAR2_PRELIM) \
234 && defined(CFG_LBLAWAR2_PRELIM)
236 * Initialize SDRAM memory on the Local Bus.
239 void sdram_init(void)
241 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
242 volatile lbus83xx_t
*lbc
= &immap
->lbus
;
243 uint
*sdram_addr
= (uint
*) CFG_LBC_SDRAM_BASE
;
246 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
248 /*setup mtrpt, lsrt and lbcr for LB bus */
249 lbc
->lbcr
= CFG_LBC_LBCR
;
250 lbc
->mrtpr
= CFG_LBC_MRTPR
;
251 lbc
->lsrt
= CFG_LBC_LSRT
;
255 * Configure the SDRAM controller Machine Mode Register.
257 lbc
->lsdmr
= CFG_LBC_LSDMR_5
; /* Normal Operation */
258 lbc
->lsdmr
= CFG_LBC_LSDMR_1
; /* Precharge All Banks */
264 * We need do 8 times auto refresh operation.
266 lbc
->lsdmr
= CFG_LBC_LSDMR_2
;
268 *sdram_addr
= 0xff; /* 1 times */
270 *sdram_addr
= 0xff; /* 2 times */
272 *sdram_addr
= 0xff; /* 3 times */
274 *sdram_addr
= 0xff; /* 4 times */
276 *sdram_addr
= 0xff; /* 5 times */
278 *sdram_addr
= 0xff; /* 6 times */
280 *sdram_addr
= 0xff; /* 7 times */
282 *sdram_addr
= 0xff; /* 8 times */
285 /* Mode register write operation */
286 lbc
->lsdmr
= CFG_LBC_LSDMR_4
;
288 *(sdram_addr
+ 0xcc) = 0xff;
291 /* Normal operation */
292 lbc
->lsdmr
= CFG_LBC_LSDMR_5
| 0x40000000;
298 void sdram_init(void)
303 #if defined(CONFIG_OF_BOARD_SETUP)
304 void ft_board_setup(void *blob
, bd_t
*bd
)
306 #if defined(CONFIG_OF_FLAT_TREE)
310 p
= ft_get_prop(blob
, "/memory/reg", &len
);
312 *p
++ = cpu_to_be32(bd
->bi_memstart
);
313 *p
= cpu_to_be32(bd
->bi_memsize
);
316 ft_cpu_setup(blob
, bd
);
318 ft_pci_setup(blob
, bd
);