2 * Copyright 2008 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
36 #include <fdt_support.h>
38 #include "../common/pixis.h"
40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
41 extern void ddr_enable_ecc(unsigned int dram_size
);
44 phys_size_t
fixed_sdram(void);
48 printf ("Board: MPC8536DS, System ID: 0x%02x, "
49 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
50 in8(PIXIS_BASE
+ PIXIS_ID
), in8(PIXIS_BASE
+ PIXIS_VER
),
51 in8(PIXIS_BASE
+ PIXIS_PVER
));
56 initdram(int board_type
)
58 phys_size_t dram_size
= 0;
60 puts("Initializing....");
62 #ifdef CONFIG_SPD_EEPROM
63 dram_size
= fsl_ddr_sdram();
65 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
67 dram_size
*= 0x100000;
69 dram_size
= fixed_sdram();
72 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
74 * Initialize and enable DDR ECC.
76 ddr_enable_ecc(dram_size
);
82 #if !defined(CONFIG_SPD_EEPROM)
84 * Fixed sdram init -- doesn't use serial presence detect.
87 phys_size_t
fixed_sdram (void)
89 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
90 volatile ccsr_ddr_t
*ddr
= &immap
->im_ddr
;
93 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS
;
94 ddr
->cs0_config
= CONFIG_SYS_DDR_CS0_CONFIG
;
96 ddr
->timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
97 ddr
->timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
98 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
99 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
100 ddr
->sdram_mode
= CONFIG_SYS_DDR_MODE_1
;
101 ddr
->sdram_mode_2
= CONFIG_SYS_DDR_MODE_2
;
102 ddr
->sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
103 ddr
->sdram_data_init
= CONFIG_SYS_DDR_DATA_INIT
;
104 ddr
->sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL
;
105 ddr
->sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL2
;
107 #if defined (CONFIG_DDR_ECC)
108 ddr
->err_int_en
= CONFIG_SYS_DDR_ERR_INT_EN
;
109 ddr
->err_disable
= CONFIG_SYS_DDR_ERR_DIS
;
110 ddr
->err_sbe
= CONFIG_SYS_DDR_SBE
;
116 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
118 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
120 debug("DDR - 1st controller: memory initializing\n");
122 * Poll until memory is initialized.
123 * 512 Meg at 400 might hit this 200 times or so.
125 while ((ddr
->sdram_cfg_2
& (d_init
<< 4)) != 0) {
128 debug("DDR: memory initialized\n\n");
133 return 512 * 1024 * 1024;
139 static struct pci_controller pci1_hose
;
143 static struct pci_controller pcie1_hose
;
147 static struct pci_controller pcie2_hose
;
151 static struct pci_controller pcie3_hose
;
154 int first_free_busno
=0;
159 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
160 uint devdisr
= gur
->devdisr
;
162 (gur
->pordevsr
& MPC85xx_PORDEVSR_SRDS2_IO_SEL
) >> 27;
163 uint io_sel
= (gur
->pordevsr
& MPC85xx_PORDEVSR_IO_SEL
) >> 19;
164 uint host_agent
= (gur
->porbmsr
& MPC85xx_PORBMSR_HA
) >> 16;
166 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
167 host_agent=%x\n", devdisr
, sdrs2_io_sel
, io_sel
, host_agent
);
169 if (sdrs2_io_sel
== 7)
170 printf(" Serdes2 disalbed\n");
171 else if (sdrs2_io_sel
== 4) {
172 printf(" eTSEC1 is in sgmii mode.\n");
173 printf(" eTSEC3 is in sgmii mode.\n");
174 } else if (sdrs2_io_sel
== 6)
175 printf(" eTSEC1 is in sgmii mode.\n");
179 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE3_ADDR
;
180 extern void fsl_pci_init(struct pci_controller
*hose
);
181 struct pci_controller
*hose
= &pcie3_hose
;
182 int pcie_ep
= (host_agent
== 1);
183 int pcie_configured
= (io_sel
== 7);
185 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
186 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
187 pcie_ep
? "End Point" : "Root Complex",
189 if (pci
->pme_msg_det
) {
190 pci
->pme_msg_det
= 0xffffffff;
191 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
196 pci_set_region(hose
->regions
+ 0,
197 CONFIG_SYS_PCI_MEMORY_BUS
,
198 CONFIG_SYS_PCI_MEMORY_PHYS
,
199 CONFIG_SYS_PCI_MEMORY_SIZE
,
200 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
202 /* outbound memory */
203 pci_set_region(hose
->regions
+ 1,
204 CONFIG_SYS_PCIE3_MEM_BASE
,
205 CONFIG_SYS_PCIE3_MEM_PHYS
,
206 CONFIG_SYS_PCIE3_MEM_SIZE
,
210 pci_set_region(hose
->regions
+ 2,
211 CONFIG_SYS_PCIE3_IO_BASE
,
212 CONFIG_SYS_PCIE3_IO_PHYS
,
213 CONFIG_SYS_PCIE3_IO_SIZE
,
216 hose
->region_count
= 3;
218 hose
->first_busno
=first_free_busno
;
219 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
223 first_free_busno
=hose
->last_busno
+1;
224 printf (" PCIE3 on bus %02x - %02x\n",
225 hose
->first_busno
,hose
->last_busno
);
227 printf (" PCIE3: disabled\n");
232 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE3
; /* disable */
237 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE1_ADDR
;
238 extern void fsl_pci_init(struct pci_controller
*hose
);
239 struct pci_controller
*hose
= &pcie1_hose
;
240 int pcie_ep
= (host_agent
== 5);
241 int pcie_configured
= (io_sel
== 2 || io_sel
== 3
242 || io_sel
== 5 || io_sel
== 7);
244 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
245 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
246 pcie_ep
? "End Point" : "Root Complex",
248 if (pci
->pme_msg_det
) {
249 pci
->pme_msg_det
= 0xffffffff;
250 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
255 pci_set_region(hose
->regions
+ 0,
256 CONFIG_SYS_PCI_MEMORY_BUS
,
257 CONFIG_SYS_PCI_MEMORY_PHYS
,
258 CONFIG_SYS_PCI_MEMORY_SIZE
,
259 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
261 /* outbound memory */
262 pci_set_region(hose
->regions
+ 1,
263 CONFIG_SYS_PCIE1_MEM_BASE
,
264 CONFIG_SYS_PCIE1_MEM_PHYS
,
265 CONFIG_SYS_PCIE1_MEM_SIZE
,
269 pci_set_region(hose
->regions
+ 2,
270 CONFIG_SYS_PCIE1_IO_BASE
,
271 CONFIG_SYS_PCIE1_IO_PHYS
,
272 CONFIG_SYS_PCIE1_IO_SIZE
,
275 hose
->region_count
= 3;
276 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
277 /* outbound memory */
278 pci_set_region(hose
->regions
+ 3,
279 CONFIG_SYS_PCIE1_MEM_BASE2
,
280 CONFIG_SYS_PCIE1_MEM_PHYS2
,
281 CONFIG_SYS_PCIE1_MEM_SIZE2
,
283 hose
->region_count
++;
285 hose
->first_busno
=first_free_busno
;
287 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
291 first_free_busno
=hose
->last_busno
+1;
292 printf(" PCIE1 on bus %02x - %02x\n",
293 hose
->first_busno
,hose
->last_busno
);
296 printf (" PCIE1: disabled\n");
301 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE
; /* disable */
306 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE2_ADDR
;
307 extern void fsl_pci_init(struct pci_controller
*hose
);
308 struct pci_controller
*hose
= &pcie2_hose
;
309 int pcie_ep
= (host_agent
== 3);
310 int pcie_configured
= (io_sel
== 5 || io_sel
== 7);
312 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
313 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
314 pcie_ep
? "End Point" : "Root Complex",
316 if (pci
->pme_msg_det
) {
317 pci
->pme_msg_det
= 0xffffffff;
318 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
323 pci_set_region(hose
->regions
+ 0,
324 CONFIG_SYS_PCI_MEMORY_BUS
,
325 CONFIG_SYS_PCI_MEMORY_PHYS
,
326 CONFIG_SYS_PCI_MEMORY_SIZE
,
327 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
329 /* outbound memory */
330 pci_set_region(hose
->regions
+ 1,
331 CONFIG_SYS_PCIE2_MEM_BASE
,
332 CONFIG_SYS_PCIE2_MEM_PHYS
,
333 CONFIG_SYS_PCIE2_MEM_SIZE
,
337 pci_set_region(hose
->regions
+ 2,
338 CONFIG_SYS_PCIE2_IO_BASE
,
339 CONFIG_SYS_PCIE2_IO_PHYS
,
340 CONFIG_SYS_PCIE2_IO_SIZE
,
343 hose
->region_count
= 3;
344 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2
345 /* outbound memory */
346 pci_set_region(hose
->regions
+ 3,
347 CONFIG_SYS_PCIE2_MEM_BASE2
,
348 CONFIG_SYS_PCIE2_MEM_PHYS2
,
349 CONFIG_SYS_PCIE2_MEM_SIZE2
,
351 hose
->region_count
++;
353 hose
->first_busno
=first_free_busno
;
354 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
357 first_free_busno
=hose
->last_busno
+1;
358 printf (" PCIE2 on bus %02x - %02x\n",
359 hose
->first_busno
,hose
->last_busno
);
362 printf (" PCIE2: disabled\n");
367 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE2
; /* disable */
373 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCI1_ADDR
;
374 extern void fsl_pci_init(struct pci_controller
*hose
);
375 struct pci_controller
*hose
= &pci1_hose
;
377 uint pci_agent
= (host_agent
== 6);
378 uint pci_speed
= 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
380 uint pci_arb
= gur
->pordevsr
& MPC85xx_PORDEVSR_PCI1_ARB
; /* PORDEVSR[14] */
381 uint pci_clk_sel
= gur
->porpllsr
& MPC85xx_PORDEVSR_PCI1_SPD
; /* PORPLLSR[16] */
384 if (!(devdisr
& MPC85xx_DEVDISR_PCI1
)) {
385 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
387 (pci_speed
== 33333000) ? "33" :
388 (pci_speed
== 66666000) ? "66" : "unknown",
389 pci_clk_sel
? "sync" : "async",
390 pci_agent
? "agent" : "host",
391 pci_arb
? "arbiter" : "external-arbiter",
396 pci_set_region(hose
->regions
+ 0,
397 CONFIG_SYS_PCI_MEMORY_BUS
,
398 CONFIG_SYS_PCI_MEMORY_PHYS
,
399 CONFIG_SYS_PCI_MEMORY_SIZE
,
400 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
402 /* outbound memory */
403 pci_set_region(hose
->regions
+ 1,
404 CONFIG_SYS_PCI1_MEM_BASE
,
405 CONFIG_SYS_PCI1_MEM_PHYS
,
406 CONFIG_SYS_PCI1_MEM_SIZE
,
410 pci_set_region(hose
->regions
+ 2,
411 CONFIG_SYS_PCI1_IO_BASE
,
412 CONFIG_SYS_PCI1_IO_PHYS
,
413 CONFIG_SYS_PCI1_IO_SIZE
,
415 hose
->region_count
= 3;
416 #ifdef CONFIG_SYS_PCI1_MEM_BASE2
417 /* outbound memory */
418 pci_set_region(hose
->regions
+ 3,
419 CONFIG_SYS_PCI1_MEM_BASE2
,
420 CONFIG_SYS_PCI1_MEM_PHYS2
,
421 CONFIG_SYS_PCI1_MEM_SIZE2
,
423 hose
->region_count
++;
425 hose
->first_busno
=first_free_busno
;
426 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
429 first_free_busno
=hose
->last_busno
+1;
430 printf ("PCI on bus %02x - %02x\n",
431 hose
->first_busno
,hose
->last_busno
);
433 printf (" PCI: disabled\n");
437 gur
->devdisr
|= MPC85xx_DEVDISR_PCI1
; /* disable */
442 int board_early_init_r(void)
445 const unsigned int flashbase
= CONFIG_SYS_FLASH_BASE
;
446 const u8 flash_esel
= 1;
449 * Remap Boot flash + PROMJET region to caching-inhibited
450 * so that flash can be erased properly.
453 /* Invalidate any remaining lines of the flash from caches. */
454 for (i
= 0; i
< 256*1024*1024; i
+=32) {
455 asm volatile ("dcbi %0,%1": : "b" (flashbase
), "r" (i
));
456 asm volatile ("icbi %0,%1": : "b" (flashbase
), "r" (i
));
459 /* invalidate existing TLB entry for flash + promjet */
460 disable_tlb(flash_esel
);
462 set_tlb(1, flashbase
, flashbase
, /* tlb, epn, rpn */
463 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
, /* perms, wimge */
464 0, flash_esel
, BOOKE_PAGESZ_256M
, 1); /* ts, esel, tsize, iprot */
469 #ifdef CONFIG_GET_CLK_FROM_ICS307
470 /* decode S[0-2] to Output Divider (OD) */
473 10, 2, 8, 4, 5, 7, 3, 6
476 /* Calculate frequency being generated by ICS307-02 clock chip based upon
477 * the control bytes being programmed into it. */
478 /* XXX: This function should probably go into a common library */
480 ics307_clk_freq (unsigned char cw0
, unsigned char cw1
, unsigned char cw2
)
482 const unsigned long long InputFrequency
= CONFIG_ICS307_REFCLK_HZ
;
483 unsigned long VDW
= ((cw1
<< 1) & 0x1FE) + ((cw2
>> 7) & 1);
484 unsigned long RDW
= cw2
& 0x7F;
485 unsigned long OD
= ics307_S_to_OD
[cw0
& 0x7];
488 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
490 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
491 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
492 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
494 * R6:R0 = Reference Divider Word (RDW)
495 * V8:V0 = VCO Divider Word (VDW)
496 * S2:S0 = Output Divider Select (OD)
497 * F1:F0 = Function of CLK2 Output
499 * C1:C0 = internal load capacitance for cyrstal
502 /* Adding 1 to get a "nicely" rounded number, but this needs
503 * more tweaking to get a "properly" rounded number. */
505 freq
= 1 + (InputFrequency
* 2 * (VDW
+ 8) / ((RDW
+ 2) * OD
));
507 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0
, cw1
, cw2
,
513 get_board_sys_clk(ulong dummy
)
515 return ics307_clk_freq (
516 in8(PIXIS_BASE
+ PIXIS_VSYSCLK0
),
517 in8(PIXIS_BASE
+ PIXIS_VSYSCLK1
),
518 in8(PIXIS_BASE
+ PIXIS_VSYSCLK2
)
523 get_board_ddr_clk(ulong dummy
)
525 return ics307_clk_freq (
526 in8(PIXIS_BASE
+ PIXIS_VDDRCLK0
),
527 in8(PIXIS_BASE
+ PIXIS_VDDRCLK1
),
528 in8(PIXIS_BASE
+ PIXIS_VDDRCLK2
)
533 get_board_sys_clk(ulong dummy
)
538 i
= in8(PIXIS_BASE
+ PIXIS_SPD
);
572 get_board_ddr_clk(ulong dummy
)
577 i
= in8(PIXIS_BASE
+ PIXIS_SPD
);
611 int is_sata_supported(void)
613 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
614 uint devdisr
= gur
->devdisr
;
616 (gur
->pordevsr
& MPC85xx_PORDEVSR_SRDS2_IO_SEL
) >> 27;
617 if (sdrs2_io_sel
& 0x04)
623 #if defined(CONFIG_OF_BOARD_SETUP)
625 ft_board_setup(void *blob
, bd_t
*bd
)
630 ft_cpu_setup(blob
, bd
);
632 node
= fdt_path_offset(blob
, "/aliases");
636 path
= fdt_getprop(blob
, node
, "pci0", NULL
);
638 tmp
[1] = pci1_hose
.last_busno
- pci1_hose
.first_busno
;
639 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
643 path
= fdt_getprop(blob
, node
, "pci1", NULL
);
645 tmp
[1] = pcie2_hose
.last_busno
- pcie2_hose
.first_busno
;
646 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
650 path
= fdt_getprop(blob
, node
, "pci2", NULL
);
652 tmp
[1] = pcie1_hose
.last_busno
- pcie1_hose
.first_busno
;
653 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
657 path
= fdt_getprop(blob
, node
, "pci3", NULL
);
659 tmp
[1] = pcie3_hose
.last_busno
- pcie3_hose
.first_busno
;
660 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);