board/freescale/mpc8555cds/mpc8555cds.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25 #include <asm/processor.h>
  26 #include <asm/mmu.h>
  27 #include <asm/immap_85xx.h>
  28 #include <asm/fsl_ddr_sdram.h>
  29 #include <ioports.h>
  30 #include <spd_sdram.h>
  31 #include <libfdt.h>
  32 #include <fdt_support.h>
  33
  34 #include "../common/cadmus.h"
  35 #include "../common/eeprom.h"
  36 #include "../common/via.h"
  37
  38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  39 extern void ddr_enable_ecc(unsigned int dram_size);
  40 #endif
  41
  42 void local_bus_init(void);
  43 void sdram_init(void);
  44
  45 /*
  46  * I/O Port configuration table
  47  *
  48  * if conf is 1, then that port pin will be configured at boot time
  49  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  50  */
  51
  52 const iop_conf_t iop_conf_tab[4][32] = {
  53
  54     /* Port A configuration */
  55     {   /*            conf ppar psor pdir podr pdat */
  56         /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  57         /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  58         /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  59         /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  60         /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  61         /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  62         /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  63         /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  64         /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  65         /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  66         /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  67         /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  68         /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  69         /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  70         /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  71         /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  72         /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  73         /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  74         /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  75         /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  76         /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  77         /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  78         /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  79         /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  80         /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  81         /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  82         /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  83         /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  84         /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  85         /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  86         /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  87         /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  88     },
  89
  90     /* Port B configuration */
  91     {   /*            conf ppar psor pdir podr pdat */
  92         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  93         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  94         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  95         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  96         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  97         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  98         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  99         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
 100         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
 101         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
 102         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
 103         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 104         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 105         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 106         /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 107         /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 108         /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 109         /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 110         /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 111         /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 112         /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 113         /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 114         /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 115         /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 116         /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 117         /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 118         /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 119         /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 120         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 121         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 122         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 123         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 124     },
 125
 126     /* Port C */
 127     {   /*            conf ppar psor pdir podr pdat */
 128         /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 129         /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 130         /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 131         /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 132         /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 133         /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 134         /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 135         /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 136         /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 137         /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 138         /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 139         /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 140         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 141         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 142         /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 143         /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 144         /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 145         /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 146         /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 147         /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 148         /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 149         /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 150         /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 151         /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 152         /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 153         /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 154         /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 155         /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 156         /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 157         /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 158         /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 159         /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 160     },
 161
 162     /* Port D */
 163     {   /*            conf ppar psor pdir podr pdat */
 164         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 165         /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 166         /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 167         /* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
 168         /* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
 169         /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 170         /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 171         /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 172         /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 173         /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 174         /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 175         /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 176         /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 177         /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 178         /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 179         /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 180         /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 181         /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 182         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 183         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 184         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 185         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 186         /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 187         /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 188         /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 189         /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 190         /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 191         /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 192         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 193         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 194         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 195         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 196     }
 197 };
 198
 199 int checkboard (void)
 200 {
 201         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 202
 203         /* PCI slot in USER bits CSR[6:7] by convention. */
 204         uint pci_slot = get_pci_slot ();
 205
 206         uint pci_dual = get_pci_dual ();        /* PCI DUAL in CM_PCI[3] */
 207         uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
 208         uint pci1_clk_sel = gur->porpllsr & 0x8000;     /* PORPLLSR[16] */
 209         uint pci2_clk_sel = gur->porpllsr & 0x4000;     /* PORPLLSR[17] */
 210
 211         uint pci1_speed = get_clock_freq ();    /* PCI PSPEED in [4:5] */
 212
 213         uint cpu_board_rev = get_cpu_board_revision ();
 214
 215         printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
 216                 get_board_version (), pci_slot);
 217
 218         printf ("CPU Board Revision %d.%d (0x%04x)\n",
 219                 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
 220                 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
 221
 222         printf ("    PCI1: %d bit, %s MHz, %s\n",
 223                 (pci1_32) ? 32 : 64,
 224                 (pci1_speed == 33000000) ? "33" :
 225                 (pci1_speed == 66000000) ? "66" : "unknown",
 226                 pci1_clk_sel ? "sync" : "async");
 227
 228         if (pci_dual) {
 229                 printf ("    PCI2: 32 bit, 66 MHz, %s\n",
 230                         pci2_clk_sel ? "sync" : "async");
 231         } else {
 232                 printf ("    PCI2: disabled\n");
 233         }
 234
 235         /*
 236          * Initialize local bus.
 237          */
 238         local_bus_init ();
 239
 240         return 0;
 241 }
 242
 243 phys_size_t
 244 initdram(int board_type)
 245 {
 246         long dram_size = 0;
 247
 248         puts("Initializing\n");
 249
 250 #if defined(CONFIG_DDR_DLL)
 251         {
 252                 /*
 253                  * Work around to stabilize DDR DLL MSYNC_IN.
 254                  * Errata DDR9 seems to have been fixed.
 255                  * This is now the workaround for Errata DDR11:
 256                  *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 257                  */
 258
 259                 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 260
 261                 gur->ddrdllcr = 0x81000000;
 262                 asm("sync;isync;msync");
 263                 udelay(200);
 264         }
 265 #endif
 266
 267         dram_size = fsl_ddr_sdram();
 268         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 269         dram_size *= 0x100000;
 270
 271 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 272         /*
 273          * Initialize and enable DDR ECC.
 274          */
 275         ddr_enable_ecc(dram_size);
 276 #endif
 277
 278         /*
 279          * SDRAM Initialization
 280          */
 281         sdram_init();
 282
 283         puts("    DDR: ");
 284         return dram_size;
 285 }
 286
 287 /*
 288  * Initialize Local Bus
 289  */
 290 void
 291 local_bus_init(void)
 292 {
 293         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 294         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 295
 296         uint clkdiv;
 297         uint lbc_hz;
 298         sys_info_t sysinfo;
 299         uint temp_lbcdll;
 300
 301         /*
 302          * Errata LBC11.
 303          * Fix Local Bus clock glitch when DLL is enabled.
 304          *
 305          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 306          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 307          * Between 66 and 133, the DLL is enabled with an override workaround.
 308          */
 309
 310         get_sys_info(&sysinfo);
 311         clkdiv = lbc->lcrr & 0x0f;
 312         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 313
 314         if (lbc_hz < 66) {
 315                 lbc->lcrr |= 0x80000000;        /* DLL Bypass */
 316
 317         } else if (lbc_hz >= 133) {
 318                 lbc->lcrr &= (~0x80000000);             /* DLL Enabled */
 319
 320         } else {
 321                 lbc->lcrr &= (~0x8000000);      /* DLL Enabled */
 322                 udelay(200);
 323
 324                 /*
 325                  * Sample LBC DLL ctrl reg, upshift it to set the
 326                  * override bits.
 327                  */
 328                 temp_lbcdll = gur->lbcdllcr;
 329                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 330                 asm("sync;isync;msync");
 331         }
 332 }
 333
 334 /*
 335  * Initialize SDRAM memory on the Local Bus.
 336  */
 337 void
 338 sdram_init(void)
 339 {
 340 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 341
 342         uint idx;
 343         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 344         uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 345         uint cpu_board_rev;
 346         uint lsdmr_common;
 347
 348         puts("    SDRAM: ");
 349
 350         print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 351
 352         /*
 353          * Setup SDRAM Base and Option Registers
 354          */
 355         lbc->or2 = CONFIG_SYS_OR2_PRELIM;
 356         asm("msync");
 357
 358         lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 359         asm("msync");
 360
 361         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 362         asm("msync");
 363
 364         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 365         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 366         asm("msync");
 367
 368         /*
 369          * Determine which address lines to use baed on CPU board rev.
 370          */
 371         cpu_board_rev = get_cpu_board_revision();
 372         lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 373         if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
 374                 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
 375         } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
 376                 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
 377         } else {
 378                 /*
 379                  * Assume something unable to identify itself is
 380                  * really old, and likely has lines 16/17 mapped.
 381                  */
 382                 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
 383         }
 384
 385         /*
 386          * Issue PRECHARGE ALL command.
 387          */
 388         lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
 389         asm("sync;msync");
 390         *sdram_addr = 0xff;
 391         ppcDcbf((unsigned long) sdram_addr);
 392         udelay(100);
 393
 394         /*
 395          * Issue 8 AUTO REFRESH commands.
 396          */
 397         for (idx = 0; idx < 8; idx++) {
 398                 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
 399                 asm("sync;msync");
 400                 *sdram_addr = 0xff;
 401                 ppcDcbf((unsigned long) sdram_addr);
 402                 udelay(100);
 403         }
 404
 405         /*
 406          * Issue 8 MODE-set command.
 407          */
 408         lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
 409         asm("sync;msync");
 410         *sdram_addr = 0xff;
 411         ppcDcbf((unsigned long) sdram_addr);
 412         udelay(100);
 413
 414         /*
 415          * Issue NORMAL OP command.
 416          */
 417         lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
 418         asm("sync;msync");
 419         *sdram_addr = 0xff;
 420         ppcDcbf((unsigned long) sdram_addr);
 421         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 422
 423 #endif  /* enable SDRAM init */
 424 }
 425
 426 #ifdef CONFIG_PCI
 427 /* For some reason the Tundra PCI bridge shows up on itself as a
 428  * different device.  Work around that by refusing to configure it
 429  */
 430 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
 431
 432 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 433         {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 434         {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
 435         {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 436                 mpc85xx_config_via_usbide, {0,0,0}},
 437         {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
 438                 mpc85xx_config_via_usb, {0,0,0}},
 439         {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
 440                 mpc85xx_config_via_usb2, {0,0,0}},
 441         {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 442                 mpc85xx_config_via_power, {0,0,0}},
 443         {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
 444                 mpc85xx_config_via_ac97, {0,0,0}},
 445         {},
 446 };
 447
 448
 449 static struct pci_controller hose[] = {
 450         {
 451         config_table: pci_mpc85xxcds_config_table,
 452         },
 453 #ifdef CONFIG_MPC85XX_PCI2
 454         {},
 455 #endif
 456 };
 457
 458 #endif
 459
 460 void
 461 pci_init_board(void)
 462 {
 463 #ifdef CONFIG_PCI
 464         pci_mpc85xx_init(hose);
 465 #endif
 466 }
 467
 468 #if defined(CONFIG_OF_BOARD_SETUP)
 469 void
 470 ft_pci_setup(void *blob, bd_t *bd)
 471 {
 472         int node, tmp[2];
 473         const char *path;
 474
 475         node = fdt_path_offset(blob, "/aliases");
 476         tmp[0] = 0;
 477         if (node >= 0) {
 478 #ifdef CONFIG_PCI1
 479                 path = fdt_getprop(blob, node, "pci0", NULL);
 480                 if (path) {
 481                         tmp[1] = hose[0].last_busno - hose[0].first_busno;
 482                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 483                 }
 484 #endif
 485 #ifdef CONFIG_MPC85XX_PCI2
 486                 path = fdt_getprop(blob, node, "pci1", NULL);
 487                 if (path) {
 488                         tmp[1] = hose[1].last_busno - hose[1].first_busno;
 489                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 490                 }
 491 #endif
 492         }
 493 }
 494 #endif