2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_86xx.h>
28 #include <asm/immap_fsl_pci.h>
29 #include <asm/fsl_ddr_sdram.h>
33 #include <fdt_support.h>
34 #include <spd_sdram.h>
37 #include "../common/pixis.h"
39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
40 extern void ddr_enable_ecc(unsigned int dram_size
);
43 void sdram_init(void);
44 long int fixed_sdram(void);
45 void mpc8610hpcd_diu_init(void);
48 /* called before any console output */
49 int board_early_init_f(void)
51 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
52 volatile ccsr_gur_t
*gur
= &immap
->im_gur
;
54 gur
->gpiocr
|= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
63 /*Do not use 8259PIC*/
64 tmp_val
= in8(PIXIS_BASE
+ PIXIS_BRDCFG0
);
65 out8(PIXIS_BASE
+ PIXIS_BRDCFG0
, tmp_val
| 0x80);
67 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
68 version
= in8(PIXIS_BASE
+ PIXIS_PVER
);
70 tmp_val
= in8(PIXIS_BASE
+ PIXIS_BRDCFG0
);
71 out8(PIXIS_BASE
+ PIXIS_BRDCFG0
, tmp_val
& 0xbf);
74 /* Using this for DIU init before the driver in linux takes over
75 * Enable the TFP410 Encoder (I2C address 0x38)
79 i2c_write(0x38, 0x08, 1, &tmp_val
, sizeof(tmp_val
));
80 /* Verify if enabled */
82 i2c_read(0x38, 0x08, 1, &tmp_val
, sizeof(tmp_val
));
83 debug("DVI Encoder Read: 0x%02lx\n",tmp_val
);
86 i2c_write(0x38, 0x0A, 1, &tmp_val
, sizeof(tmp_val
));
87 /* Verify if enabled */
89 i2c_read(0x38, 0x0A, 1, &tmp_val
, sizeof(tmp_val
));
90 debug("DVI Encoder Read: 0x%02lx\n",tmp_val
);
92 #ifdef CONFIG_FSL_DIU_FB
93 mpc8610hpcd_diu_init();
101 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
102 volatile ccsr_local_mcm_t
*mcm
= &immap
->im_local_mcm
;
104 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
105 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
106 in8(PIXIS_BASE
+ PIXIS_ID
), in8(PIXIS_BASE
+ PIXIS_VER
),
107 in8(PIXIS_BASE
+ PIXIS_PVER
));
109 mcm
->abcr
|= 0x00010000; /* 0 */
110 mcm
->hpmr3
= 0x80000008; /* 4c */
122 initdram(int board_type
)
126 #if defined(CONFIG_SPD_EEPROM)
127 dram_size
= fsl_ddr_sdram();
129 dram_size
= fixed_sdram();
132 #if defined(CONFIG_SYS_RAMBOOT)
137 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
139 * Initialize and enable DDR ECC.
141 ddr_enable_ecc(dram_size
);
149 #if !defined(CONFIG_SPD_EEPROM)
151 * Fixed sdram init -- doesn't use serial presence detect.
154 long int fixed_sdram(void)
156 #if !defined(CONFIG_SYS_RAMBOOT)
157 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
158 volatile ccsr_ddr_t
*ddr
= &immap
->im_ddr1
;
161 ddr
->cs0_bnds
= 0x0000001f;
162 ddr
->cs0_config
= 0x80010202;
164 ddr
->timing_cfg_3
= 0x00000000;
165 ddr
->timing_cfg_0
= 0x00260802;
166 ddr
->timing_cfg_1
= 0x3935d322;
167 ddr
->timing_cfg_2
= 0x14904cc8;
168 ddr
->sdram_mode_1
= 0x00480432;
169 ddr
->sdram_mode_2
= 0x00000000;
170 ddr
->sdram_interval
= 0x06180fff; /* 0x06180100; */
171 ddr
->sdram_data_init
= 0xDEADBEEF;
172 ddr
->sdram_clk_cntl
= 0x03800000;
173 ddr
->sdram_cfg_2
= 0x04400010;
175 #if defined(CONFIG_DDR_ECC)
176 ddr
->err_int_en
= 0x0000000d;
177 ddr
->err_disable
= 0x00000000;
178 ddr
->err_sbe
= 0x00010000;
184 ddr
->sdram_cfg_1
= 0xc3000000; /* 0xe3008000;*/
187 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
189 debug("DDR - 1st controller: memory initializing\n");
191 * Poll until memory is initialized.
192 * 512 Meg at 400 might hit this 200 times or so.
194 while ((ddr
->sdram_cfg_2
& (d_init
<< 4)) != 0)
197 debug("DDR: memory initialized\n\n");
202 return 512 * 1024 * 1024;
204 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
209 #if defined(CONFIG_PCI)
211 * Initialize PCI Devices, report devices found.
214 #ifndef CONFIG_PCI_PNP
215 static struct pci_config_table pci_fsl86xxads_config_table
[] = {
216 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
217 PCI_IDSEL_NUMBER
, PCI_ANY_ID
,
218 pci_cfgfunc_config_device
, {PCI_ENET0_IOADDR
,
220 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
} },
226 static struct pci_controller pci1_hose
= {
227 #ifndef CONFIG_PCI_PNP
228 config_table
:pci_mpc86xxcts_config_table
231 #endif /* CONFIG_PCI */
234 static struct pci_controller pcie1_hose
;
238 static struct pci_controller pcie2_hose
;
241 int first_free_busno
= 0;
243 void pci_init_board(void)
245 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_CCSRBAR
;
246 volatile ccsr_gur_t
*gur
= &immap
->im_gur
;
247 uint devdisr
= gur
->devdisr
;
248 uint io_sel
= (gur
->pordevsr
& MPC8610_PORDEVSR_IO_SEL
)
249 >> MPC8610_PORDEVSR_IO_SEL_SHIFT
;
250 uint host_agent
= (gur
->porbmsr
& MPC8610_PORBMSR_HA
)
251 >> MPC8610_PORBMSR_HA_SHIFT
;
253 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
254 devdisr
, io_sel
, host_agent
);
258 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE1_ADDR
;
259 extern void fsl_pci_init(struct pci_controller
*hose
);
260 struct pci_controller
*hose
= &pcie1_hose
;
261 int pcie_configured
= (io_sel
== 1) || (io_sel
== 4);
262 int pcie_ep
= (host_agent
== 0) || (host_agent
== 2) ||
265 if (pcie_configured
&& !(devdisr
& MPC86xx_DEVDISR_PCIE1
)) {
266 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
267 pcie_ep
? "End Point" : "Root Complex",
269 if (pci
->pme_msg_det
)
270 pci
->pme_msg_det
= 0xffffffff;
273 pci_set_region(hose
->regions
+ 0,
274 CONFIG_SYS_PCI_MEMORY_BUS
,
275 CONFIG_SYS_PCI_MEMORY_PHYS
,
276 CONFIG_SYS_PCI_MEMORY_SIZE
,
277 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
279 /* outbound memory */
280 pci_set_region(hose
->regions
+ 1,
281 CONFIG_SYS_PCIE1_MEM_BASE
,
282 CONFIG_SYS_PCIE1_MEM_PHYS
,
283 CONFIG_SYS_PCIE1_MEM_SIZE
,
287 pci_set_region(hose
->regions
+ 2,
288 CONFIG_SYS_PCIE1_IO_BASE
,
289 CONFIG_SYS_PCIE1_IO_PHYS
,
290 CONFIG_SYS_PCIE1_IO_SIZE
,
293 hose
->region_count
= 3;
295 hose
->first_busno
= first_free_busno
;
296 pci_setup_indirect(hose
, (int)&pci
->cfg_addr
,
297 (int)&pci
->cfg_data
);
301 first_free_busno
= hose
->last_busno
+ 1;
302 printf(" PCI-Express 1 on bus %02x - %02x\n",
303 hose
->first_busno
, hose
->last_busno
);
306 puts(" PCI-Express 1: Disabled\n");
309 puts("PCI-Express 1: Disabled\n");
310 #endif /* CONFIG_PCIE1 */
315 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE2_ADDR
;
316 extern void fsl_pci_init(struct pci_controller
*hose
);
317 struct pci_controller
*hose
= &pcie2_hose
;
319 int pcie_configured
= (io_sel
== 0) || (io_sel
== 4);
320 int pcie_ep
= (host_agent
== 0) || (host_agent
== 1) ||
323 if (pcie_configured
&& !(devdisr
& MPC86xx_DEVDISR_PCIE2
)) {
324 printf(" PCI-Express 2 connected to slot as %s" \
325 " (base address %x)\n",
326 pcie_ep
? "End Point" : "Root Complex",
328 if (pci
->pme_msg_det
)
329 pci
->pme_msg_det
= 0xffffffff;
332 pci_set_region(hose
->regions
+ 0,
333 CONFIG_SYS_PCI_MEMORY_BUS
,
334 CONFIG_SYS_PCI_MEMORY_PHYS
,
335 CONFIG_SYS_PCI_MEMORY_SIZE
,
336 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
338 /* outbound memory */
339 pci_set_region(hose
->regions
+ 1,
340 CONFIG_SYS_PCIE2_MEM_BASE
,
341 CONFIG_SYS_PCIE2_MEM_PHYS
,
342 CONFIG_SYS_PCIE2_MEM_SIZE
,
346 pci_set_region(hose
->regions
+ 2,
347 CONFIG_SYS_PCIE2_IO_BASE
,
348 CONFIG_SYS_PCIE2_IO_PHYS
,
349 CONFIG_SYS_PCIE2_IO_SIZE
,
352 hose
->region_count
= 3;
354 hose
->first_busno
= first_free_busno
;
355 pci_setup_indirect(hose
, (int)&pci
->cfg_addr
,
356 (int)&pci
->cfg_data
);
360 first_free_busno
= hose
->last_busno
+ 1;
361 printf(" PCI-Express 2 on bus %02x - %02x\n",
362 hose
->first_busno
, hose
->last_busno
);
364 puts(" PCI-Express 2: Disabled\n");
367 puts("PCI-Express 2: Disabled\n");
368 #endif /* CONFIG_PCIE2 */
373 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCI1_ADDR
;
374 extern void fsl_pci_init(struct pci_controller
*hose
);
375 struct pci_controller
*hose
= &pci1_hose
;
376 int pci_agent
= (host_agent
>= 4) && (host_agent
<= 6);
378 if ( !(devdisr
& MPC86xx_DEVDISR_PCI1
)) {
379 printf(" PCI connected to PCI slots as %s" \
380 " (base address %x)\n",
381 pci_agent
? "Agent" : "Host",
385 pci_set_region(hose
->regions
+ 0,
386 CONFIG_SYS_PCI_MEMORY_BUS
,
387 CONFIG_SYS_PCI_MEMORY_PHYS
,
388 CONFIG_SYS_PCI_MEMORY_SIZE
,
389 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
391 /* outbound memory */
392 pci_set_region(hose
->regions
+ 1,
393 CONFIG_SYS_PCI1_MEM_BASE
,
394 CONFIG_SYS_PCI1_MEM_PHYS
,
395 CONFIG_SYS_PCI1_MEM_SIZE
,
399 pci_set_region(hose
->regions
+ 2,
400 CONFIG_SYS_PCI1_IO_BASE
,
401 CONFIG_SYS_PCI1_IO_PHYS
,
402 CONFIG_SYS_PCI1_IO_SIZE
,
405 hose
->region_count
= 3;
407 hose
->first_busno
= first_free_busno
;
408 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
,
409 (int) &pci
->cfg_data
);
413 first_free_busno
= hose
->last_busno
+ 1;
414 printf(" PCI on bus %02x - %02x\n",
415 hose
->first_busno
, hose
->last_busno
);
419 puts(" PCI: Disabled\n");
421 #endif /* CONFIG_PCI1 */
424 #if defined(CONFIG_OF_BOARD_SETUP)
426 ft_board_setup(void *blob
, bd_t
*bd
)
431 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
432 "timebase-frequency", bd
->bi_busfreq
/ 4, 1);
433 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
434 "bus-frequency", bd
->bi_busfreq
, 1);
435 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
436 "clock-frequency", bd
->bi_intfreq
, 1);
437 do_fixup_by_prop_u32(blob
, "device_type", "soc", 4,
438 "bus-frequency", bd
->bi_busfreq
, 1);
440 do_fixup_by_compat_u32(blob
, "ns16550",
441 "clock-frequency", bd
->bi_busfreq
, 1);
443 fdt_fixup_memory(blob
, bd
->bi_memstart
, bd
->bi_memsize
);
446 node
= fdt_path_offset(blob
, "/aliases");
451 path
= fdt_getprop(blob
, node
, "pci0", NULL
);
453 tmp
[1] = pci1_hose
.last_busno
- pci1_hose
.first_busno
;
454 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
459 path
= fdt_getprop(blob
, node
, "pci1", NULL
);
461 tmp
[1] = pcie1_hose
.last_busno
462 - pcie1_hose
.first_busno
;
463 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
467 path
= fdt_getprop(blob
, node
, "pci2", NULL
);
469 tmp
[1] = pcie2_hose
.last_busno
470 - pcie2_hose
.first_busno
;
471 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
480 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
484 get_board_sys_clk(ulong dummy
)
490 a
= PIXIS_BASE
+ PIXIS_SPD
;
524 int board_eth_init(bd_t
*bis
)
526 return pci_eth_init(bis
);