board/freescale/mx53evk/mx53evk.c

   1 /*
   2  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <i2c.h>
  33 #include <mmc.h>
  34 #include <fsl_esdhc.h>
  35 #include <fsl_pmic.h>
  36 #include <mxc_gpio.h>
  37 #include <mc13892.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 u32 get_board_rev(void)
  42 {
  43         return get_cpu_rev();
  44 }
  45
  46 int dram_init(void)
  47 {
  48         /* dram_init must store complete ramsize in gd->ram_size */
  49         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  50                                 PHYS_SDRAM_1_SIZE);
  51         return 0;
  52 }
  53
  54 static void setup_iomux_uart(void)
  55 {
  56         /* UART1 RXD */
  57         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  58         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  59                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  60                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  61                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  62                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  63         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  64
  65         /* UART1 TXD */
  66         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  67         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  68                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  69                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  70                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  71                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  72 }
  73
  74 static void setup_i2c(unsigned int port_number)
  75 {
  76         switch (port_number) {
  77         case 0:
  78                 /* i2c1 SDA */
  79                 mxc_request_iomux(MX53_PIN_CSI0_D8,
  80                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  81                 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
  82                                 INPUT_CTL_PATH0);
  83                 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
  84                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  85                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  86                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  87                 /* i2c1 SCL */
  88                 mxc_request_iomux(MX53_PIN_CSI0_D9,
  89                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  90                 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
  91                                 INPUT_CTL_PATH0);
  92                 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
  93                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  94                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  95                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  96                 break;
  97         case 1:
  98                 /* i2c2 SDA */
  99                 mxc_request_iomux(MX53_PIN_KEY_ROW3,
 100                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 101                 mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
 102                                 INPUT_CTL_PATH0);
 103                 mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
 104                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 105                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 106                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 107
 108                 /* i2c2 SCL */
 109                 mxc_request_iomux(MX53_PIN_KEY_COL3,
 110                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 111                 mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
 112                                 INPUT_CTL_PATH0);
 113                 mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
 114                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 115                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 116                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 117                 break;
 118         default:
 119                 printf("Warning: Wrong I2C port number\n");
 120                 break;
 121         }
 122 }
 123
 124 void power_init(void)
 125 {
 126         unsigned int val;
 127
 128         /* Set VDDA to 1.25V */
 129         val = pmic_reg_read(REG_SW_2);
 130         val &= ~SWX_OUT_MASK;
 131         val |= SWX_OUT_1_25;
 132         pmic_reg_write(REG_SW_2, val);
 133
 134         /*
 135          * Need increase VCC and VDDA to 1.3V
 136          * according to MX53 IC TO2 datasheet.
 137          */
 138         if (is_soc_rev(CHIP_REV_2_0) == 0) {
 139                 /* Set VCC to 1.3V for TO2 */
 140                 val = pmic_reg_read(REG_SW_1);
 141                 val &= ~SWX_OUT_MASK;
 142                 val |= SWX_OUT_1_30;
 143                 pmic_reg_write(REG_SW_1, val);
 144
 145                 /* Set VDDA to 1.3V for TO2 */
 146                 val = pmic_reg_read(REG_SW_2);
 147                 val &= ~SWX_OUT_MASK;
 148                 val |= SWX_OUT_1_30;
 149                 pmic_reg_write(REG_SW_2, val);
 150         }
 151 }
 152
 153 static void setup_iomux_fec(void)
 154 {
 155         /*FEC_MDIO*/
 156         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
 157         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
 158                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 159                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 160                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 161         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 162
 163         /*FEC_MDC*/
 164         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 165         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 166
 167         /* FEC RXD1 */
 168         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 169         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 170                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 171
 172         /* FEC RXD0 */
 173         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 174         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 175                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 176
 177          /* FEC TXD1 */
 178         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 179         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 180
 181         /* FEC TXD0 */
 182         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 183         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 184
 185         /* FEC TX_EN */
 186         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 187         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 188
 189         /* FEC TX_CLK */
 190         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 191         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 192                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 193
 194         /* FEC RX_ER */
 195         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 196         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 197                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 198
 199         /* FEC CRS */
 200         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 201         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 202                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 203 }
 204
 205 #ifdef CONFIG_FSL_ESDHC
 206 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 207         {MMC_SDHC1_BASE_ADDR, 1},
 208         {MMC_SDHC3_BASE_ADDR, 1},
 209 };
 210
 211 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 212 {
 213         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 214
 215         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 216                 *cd = mxc_gpio_get(77); /*GPIO3_13*/
 217         else
 218                 *cd = mxc_gpio_get(75); /*GPIO3_11*/
 219
 220         return 0;
 221 }
 222
 223 int board_mmc_init(bd_t *bis)
 224 {
 225         u32 index;
 226         s32 status = 0;
 227
 228         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 229                 switch (index) {
 230                 case 0:
 231                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 232                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 233                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 234                                                 IOMUX_CONFIG_ALT0);
 235                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 236                                                 IOMUX_CONFIG_ALT0);
 237                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 238                                                 IOMUX_CONFIG_ALT0);
 239                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 240                                                 IOMUX_CONFIG_ALT0);
 241                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 242                                                 IOMUX_CONFIG_ALT1);
 243
 244                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 245                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 246                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 247                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 248                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 249                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 250                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 251                                 PAD_CTL_DRV_HIGH);
 252                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 253                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 254                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 255                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 256                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 257                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 258                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 259                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 260                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 261                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 262                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 263                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 264                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 265                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 266                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 267                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 268                         break;
 269                 case 1:
 270                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 271                                                 IOMUX_CONFIG_ALT2);
 272                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 273                                                 IOMUX_CONFIG_ALT2);
 274                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 275                                                 IOMUX_CONFIG_ALT4);
 276                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 277                                                 IOMUX_CONFIG_ALT4);
 278                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 279                                                 IOMUX_CONFIG_ALT4);
 280                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 281                                                 IOMUX_CONFIG_ALT4);
 282                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 283                                                 IOMUX_CONFIG_ALT4);
 284                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 285                                                 IOMUX_CONFIG_ALT4);
 286                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 287                                                 IOMUX_CONFIG_ALT4);
 288                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 289                                                 IOMUX_CONFIG_ALT4);
 290                         mxc_request_iomux(MX53_PIN_EIM_DA11,
 291                                                 IOMUX_CONFIG_ALT1);
 292
 293                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
 294                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 295                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 296                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 297                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
 298                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 299                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 300                                 PAD_CTL_DRV_HIGH);
 301                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
 302                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 303                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 304                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 305                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
 306                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 307                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 308                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 309                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
 310                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 311                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 312                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 313                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
 314                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 315                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 316                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 317                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
 318                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 319                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 320                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 321                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
 322                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 323                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 324                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 325                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
 326                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 327                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 328                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 329                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
 330                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 331                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 332                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 333
 334                         break;
 335                 default:
 336                         printf("Warning: you configured more ESDHC controller"
 337                                 "(%d) as supported by the board(2)\n",
 338                                 CONFIG_SYS_FSL_ESDHC_NUM);
 339                         return status;
 340                 }
 341                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 342         }
 343
 344         return status;
 345 }
 346 #endif
 347
 348 int board_early_init_f(void)
 349 {
 350         setup_iomux_uart();
 351         setup_iomux_fec();
 352
 353         return 0;
 354 }
 355
 356 int board_init(void)
 357 {
 358         gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
 359         /* address of boot parameters */
 360         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 361
 362         return 0;
 363 }
 364
 365 int board_late_init(void)
 366 {
 367         setup_i2c(1);
 368         power_init();
 369
 370         return 0;
 371 }
 372
 373 int checkboard(void)
 374 {
 375         puts("Board: MX53EVK\n");
 376
 377         return 0;
 378 }