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[people/ms/u-boot.git] / board / freescale / mx6qsabreauto / mx6qsabreauto.c
1 /*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/errno.h>
16 #include <asm/gpio.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/spi.h>
21 #include <mmc.h>
22 #include <fsl_esdhc.h>
23 #include <miiphy.h>
24 #include <netdev.h>
25 #include <asm/arch/sys_proto.h>
26 #include <i2c.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/imx-common/video.h>
29 #include <asm/arch/crm_regs.h>
30 #include <pca953x.h>
31 #include <power/pmic.h>
32 #include <power/pfuze100_pmic.h>
33 #include "../common/pfuze.h"
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47
48 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51
52 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
53 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
54 PAD_CTL_SRE_FAST)
55 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
56
57 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
58
59 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
60 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62
63 #define I2C_PMIC 1
64
65 int dram_init(void)
66 {
67 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
68
69 return 0;
70 }
71
72 static iomux_v3_cfg_t const uart4_pads[] = {
73 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
74 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
75 };
76
77 static iomux_v3_cfg_t const enet_pads[] = {
78 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 };
94
95 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
96 static struct i2c_pads_info i2c_pad_info1 = {
97 .scl = {
98 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
99 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
100 .gp = IMX_GPIO_NR(2, 30)
101 },
102 .sda = {
103 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
104 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
105 .gp = IMX_GPIO_NR(4, 13)
106 }
107 };
108
109 #ifndef CONFIG_SYS_FLASH_CFI
110 /*
111 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
112 * Compass Sensor, Accelerometer, Res Touch
113 */
114 static struct i2c_pads_info i2c_pad_info2 = {
115 .scl = {
116 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
117 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
118 .gp = IMX_GPIO_NR(1, 3)
119 },
120 .sda = {
121 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
122 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
123 .gp = IMX_GPIO_NR(3, 18)
124 }
125 };
126 #endif
127
128 static iomux_v3_cfg_t const i2c3_pads[] = {
129 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
130 };
131
132 static iomux_v3_cfg_t const port_exp[] = {
133 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
134 };
135
136 /*Define for building port exp gpio, pin starts from 0*/
137 #define PORTEXP_IO_NR(chip, pin) \
138 ((chip << 5) + pin)
139
140 /*Get the chip addr from a ioexp gpio*/
141 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
142 (gpio_nr >> 5)
143
144 /*Get the pin number from a ioexp gpio*/
145 #define PORTEXP_IO_TO_PIN(gpio_nr) \
146 (gpio_nr & 0x1f)
147
148 static int port_exp_direction_output(unsigned gpio, int value)
149 {
150 int ret;
151
152 i2c_set_bus_num(2);
153 ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
154 if (ret)
155 return ret;
156
157 ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
158 (1 << PORTEXP_IO_TO_PIN(gpio)),
159 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
160
161 if (ret)
162 return ret;
163
164 ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
165 (1 << PORTEXP_IO_TO_PIN(gpio)),
166 (value << PORTEXP_IO_TO_PIN(gpio)));
167
168 if (ret)
169 return ret;
170
171 return 0;
172 }
173
174 static iomux_v3_cfg_t const eimnor_pads[] = {
175 MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
176 MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
177 MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
178 MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
179 MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
180 MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
181 MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
182 MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
183 MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
184 MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
185 MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
186 MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
187 MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
188 MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
189 MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
190 MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
191 MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
192 MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
193 MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
194 MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
195 MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
196 MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
197 MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
198 MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
199 MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
200 MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
201 MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
202 MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
203 MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
204 MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
205 MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
206 MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
207 MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
208 MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
209 MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
210 MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
211 MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
212 MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
213 MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
214 MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
215 MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
216 MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
217 MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
218 };
219
220 static void eimnor_cs_setup(void)
221 {
222 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
223
224 writel(0x00020181, &weim_regs->cs0gcr1);
225 writel(0x00000001, &weim_regs->cs0gcr2);
226 writel(0x0a020000, &weim_regs->cs0rcr1);
227 writel(0x0000c000, &weim_regs->cs0rcr2);
228 writel(0x0804a240, &weim_regs->cs0wcr1);
229 writel(0x00000120, &weim_regs->wcr);
230
231 set_chipselect_size(CS0_128);
232 }
233
234 static void setup_iomux_eimnor(void)
235 {
236 imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
237
238 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
239
240 eimnor_cs_setup();
241 }
242
243 static void setup_iomux_enet(void)
244 {
245 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
246 }
247
248 static iomux_v3_cfg_t const usdhc3_pads[] = {
249 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
250 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
251 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
252 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
260 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
261 };
262
263 static void setup_iomux_uart(void)
264 {
265 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
266 }
267
268 #ifdef CONFIG_FSL_ESDHC
269 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
270 {USDHC3_BASE_ADDR},
271 };
272
273 int board_mmc_getcd(struct mmc *mmc)
274 {
275 gpio_direction_input(IMX_GPIO_NR(6, 15));
276 return !gpio_get_value(IMX_GPIO_NR(6, 15));
277 }
278
279 int board_mmc_init(bd_t *bis)
280 {
281 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
282
283 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
284 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
285 }
286 #endif
287
288 #ifdef CONFIG_NAND_MXS
289 static iomux_v3_cfg_t gpmi_pads[] = {
290 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
291 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
292 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
293 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
294 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
295 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
296 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
297 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
298 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
299 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
300 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
301 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
302 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
303 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
304 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
305 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
306 };
307
308 static void setup_gpmi_nand(void)
309 {
310 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
311
312 /* config gpmi nand iomux */
313 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
314
315 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
316 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
317 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
318
319 /* enable apbh clock gating */
320 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
321 }
322 #endif
323
324 static void setup_fec(void)
325 {
326 if (is_mx6dqp()) {
327 /*
328 * select ENET MAC0 TX clock from PLL
329 */
330 imx_iomux_set_gpr_register(5, 9, 1, 1);
331 enable_fec_anatop_clock(0, ENET_125MHZ);
332 }
333
334 setup_iomux_enet();
335 }
336
337 int board_eth_init(bd_t *bis)
338 {
339 setup_fec();
340
341 return cpu_eth_init(bis);
342 }
343
344 #define BOARD_REV_B 0x200
345 #define BOARD_REV_A 0x100
346
347 static int mx6sabre_rev(void)
348 {
349 /*
350 * Get Board ID information from OCOTP_GP1[15:8]
351 * i.MX6Q ARD RevA: 0x01
352 * i.MX6Q ARD RevB: 0x02
353 */
354 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
355 struct fuse_bank *bank = &ocotp->bank[4];
356 struct fuse_bank4_regs *fuse =
357 (struct fuse_bank4_regs *)bank->fuse_regs;
358 int reg = readl(&fuse->gp1);
359 int ret;
360
361 switch (reg >> 8 & 0x0F) {
362 case 0x02:
363 ret = BOARD_REV_B;
364 break;
365 case 0x01:
366 default:
367 ret = BOARD_REV_A;
368 break;
369 }
370
371 return ret;
372 }
373
374 u32 get_board_rev(void)
375 {
376 int rev = mx6sabre_rev();
377
378 return (get_cpu_rev() & ~(0xF << 8)) | rev;
379 }
380
381 #if defined(CONFIG_VIDEO_IPUV3)
382 static void disable_lvds(struct display_info_t const *dev)
383 {
384 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
385
386 clrbits_le32(&iomux->gpr[2],
387 IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
388 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
389 }
390
391 static void do_enable_hdmi(struct display_info_t const *dev)
392 {
393 disable_lvds(dev);
394 imx_enable_hdmi_phy();
395 }
396
397 struct display_info_t const displays[] = {{
398 .bus = -1,
399 .addr = 0,
400 .pixfmt = IPU_PIX_FMT_RGB666,
401 .detect = NULL,
402 .enable = NULL,
403 .mode = {
404 .name = "Hannstar-XGA",
405 .refresh = 60,
406 .xres = 1024,
407 .yres = 768,
408 .pixclock = 15385,
409 .left_margin = 220,
410 .right_margin = 40,
411 .upper_margin = 21,
412 .lower_margin = 7,
413 .hsync_len = 60,
414 .vsync_len = 10,
415 .sync = FB_SYNC_EXT,
416 .vmode = FB_VMODE_NONINTERLACED
417 } }, {
418 .bus = -1,
419 .addr = 0,
420 .pixfmt = IPU_PIX_FMT_RGB24,
421 .detect = detect_hdmi,
422 .enable = do_enable_hdmi,
423 .mode = {
424 .name = "HDMI",
425 .refresh = 60,
426 .xres = 1024,
427 .yres = 768,
428 .pixclock = 15385,
429 .left_margin = 220,
430 .right_margin = 40,
431 .upper_margin = 21,
432 .lower_margin = 7,
433 .hsync_len = 60,
434 .vsync_len = 10,
435 .sync = FB_SYNC_EXT,
436 .vmode = FB_VMODE_NONINTERLACED,
437 } } };
438 size_t display_count = ARRAY_SIZE(displays);
439
440 iomux_v3_cfg_t const backlight_pads[] = {
441 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
442 };
443
444 static void setup_iomux_backlight(void)
445 {
446 gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
447 imx_iomux_v3_setup_multiple_pads(backlight_pads,
448 ARRAY_SIZE(backlight_pads));
449 }
450
451 static void setup_display(void)
452 {
453 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
454 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
455 int reg;
456
457 setup_iomux_backlight();
458 enable_ipu_clock();
459 imx_setup_hdmi();
460
461 /* Turn on LDB_DI0 and LDB_DI1 clocks */
462 reg = readl(&mxc_ccm->CCGR3);
463 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
464 writel(reg, &mxc_ccm->CCGR3);
465
466 /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
467 reg = readl(&mxc_ccm->cs2cdr);
468 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
469 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
470 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
471 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
472 writel(reg, &mxc_ccm->cs2cdr);
473
474 reg = readl(&mxc_ccm->cscmr2);
475 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
476 writel(reg, &mxc_ccm->cscmr2);
477
478 reg = readl(&mxc_ccm->chsccdr);
479 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
480 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
481 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
482 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
483 writel(reg, &mxc_ccm->chsccdr);
484
485 reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
486 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
487 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
488 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
489 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
490 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
491 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
492 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
493 writel(reg, &iomux->gpr[2]);
494
495 reg = readl(&iomux->gpr[3]);
496 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
497 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
498 reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
499 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
500 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
501 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
502 writel(reg, &iomux->gpr[3]);
503 }
504 #endif /* CONFIG_VIDEO_IPUV3 */
505
506 /*
507 * Do not overwrite the console
508 * Use always serial for U-Boot console
509 */
510 int overwrite_console(void)
511 {
512 return 1;
513 }
514
515 int board_early_init_f(void)
516 {
517 setup_iomux_uart();
518
519 #ifdef CONFIG_NAND_MXS
520 setup_gpmi_nand();
521 #endif
522
523 return 0;
524 }
525
526 int board_init(void)
527 {
528 /* address of boot parameters */
529 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
530
531 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
532 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
533 /* I2C 3 Steer */
534 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
535 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
536 #ifndef CONFIG_SYS_FLASH_CFI
537 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
538 #endif
539 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
540 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
541
542 #ifdef CONFIG_VIDEO_IPUV3
543 setup_display();
544 #endif
545 setup_iomux_eimnor();
546 return 0;
547 }
548
549 #ifdef CONFIG_MXC_SPI
550 int board_spi_cs_gpio(unsigned bus, unsigned cs)
551 {
552 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
553 }
554 #endif
555
556 int power_init_board(void)
557 {
558 struct pmic *p;
559 unsigned int value;
560
561 p = pfuze_common_init(I2C_PMIC);
562 if (!p)
563 return -ENODEV;
564
565 if (is_mx6dqp()) {
566 /* set SW2 staby volatage 0.975V*/
567 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
568 value &= ~0x3f;
569 value |= 0x17;
570 pmic_reg_write(p, PFUZE100_SW2STBY, value);
571 }
572
573 return pfuze_mode_init(p, APS_PFM);
574 }
575
576 #ifdef CONFIG_CMD_BMODE
577 static const struct boot_mode board_boot_modes[] = {
578 /* 4 bit bus width */
579 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
580 {NULL, 0},
581 };
582 #endif
583
584 int board_late_init(void)
585 {
586 #ifdef CONFIG_CMD_BMODE
587 add_board_boot_modes(board_boot_modes);
588 #endif
589
590 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
591 setenv("board_name", "SABREAUTO");
592
593 if (is_mx6dqp())
594 setenv("board_rev", "MX6QP");
595 else if (is_mx6dq())
596 setenv("board_rev", "MX6Q");
597 else if (is_mx6sdl())
598 setenv("board_rev", "MX6DL");
599 #endif
600
601 return 0;
602 }
603
604 int checkboard(void)
605 {
606 int rev = mx6sabre_rev();
607 char *revname;
608
609 switch (rev) {
610 case BOARD_REV_B:
611 revname = "B";
612 break;
613 case BOARD_REV_A:
614 default:
615 revname = "A";
616 break;
617 }
618
619 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
620
621 return 0;
622 }
623
624 #ifdef CONFIG_USB_EHCI_MX6
625 #define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
626 #define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
627
628 iomux_v3_cfg_t const usb_otg_pads[] = {
629 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
630 };
631
632 int board_ehci_hcd_init(int port)
633 {
634 switch (port) {
635 case 0:
636 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
637 ARRAY_SIZE(usb_otg_pads));
638
639 /*
640 * Set daisy chain for otg_pin_id on 6q.
641 * For 6dl, this bit is reserved.
642 */
643 imx_iomux_set_gpr_register(1, 13, 1, 0);
644 break;
645 case 1:
646 break;
647 default:
648 printf("MXC USB port %d not yet supported\n", port);
649 return -EINVAL;
650 }
651 return 0;
652 }
653
654 int board_ehci_power(int port, int on)
655 {
656 switch (port) {
657 case 0:
658 if (on)
659 port_exp_direction_output(USB_OTG_PWR, 1);
660 else
661 port_exp_direction_output(USB_OTG_PWR, 0);
662 break;
663 case 1:
664 if (on)
665 port_exp_direction_output(USB_HOST1_PWR, 1);
666 else
667 port_exp_direction_output(USB_HOST1_PWR, 0);
668 break;
669 default:
670 printf("MXC USB port %d not yet supported\n", port);
671 return -EINVAL;
672 }
673
674 return 0;
675 }
676 #endif