2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/imx-common/iomux-v3.h>
14 #include <linux/sizes.h>
16 #include <fsl_esdhc.h>
20 #include <power/pmic.h>
21 #include <power/pfuze3000_pmic.h>
22 #include "../common/pfuze.h"
24 #include <asm/imx-common/mxc_i2c.h>
25 #include <asm/arch/crm_regs.h>
27 #include <usb/ehci-ci.h>
29 DECLARE_GLOBAL_DATA_PTR
;
31 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
32 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
34 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
35 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
37 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
38 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
40 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
42 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
43 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
45 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
46 PAD_CTL_DSE_3P3V_49OHM)
48 #define QSPI_PAD_CTRL \
49 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
51 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
53 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
54 #ifdef CONFIG_SYS_I2C_MXC
55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
57 static struct i2c_pads_info i2c_pad_info1
= {
59 .i2c_mode
= MX7D_PAD_I2C1_SCL__I2C1_SCL
| PC
,
60 .gpio_mode
= MX7D_PAD_I2C1_SCL__GPIO4_IO8
| PC
,
61 .gp
= IMX_GPIO_NR(4, 8),
64 .i2c_mode
= MX7D_PAD_I2C1_SDA__I2C1_SDA
| PC
,
65 .gpio_mode
= MX7D_PAD_I2C1_SDA__GPIO4_IO9
| PC
,
66 .gp
= IMX_GPIO_NR(4, 9),
73 gd
->ram_size
= PHYS_SDRAM_SIZE
;
78 static iomux_v3_cfg_t
const wdog_pads
[] = {
79 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B
| MUX_PAD_CTRL(NO_PAD_CTRL
),
82 static iomux_v3_cfg_t
const uart1_pads
[] = {
83 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
84 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
87 static iomux_v3_cfg_t
const usdhc1_pads
[] = {
88 MX7D_PAD_SD1_CLK__SD1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
89 MX7D_PAD_SD1_CMD__SD1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
90 MX7D_PAD_SD1_DATA0__SD1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
91 MX7D_PAD_SD1_DATA1__SD1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
92 MX7D_PAD_SD1_DATA2__SD1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
93 MX7D_PAD_SD1_DATA3__SD1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
95 MX7D_PAD_SD1_CD_B__GPIO5_IO0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
96 MX7D_PAD_SD1_RESET_B__GPIO5_IO2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
99 static iomux_v3_cfg_t
const usdhc3_emmc_pads
[] = {
100 MX7D_PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
101 MX7D_PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
102 MX7D_PAD_SD3_DATA0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
103 MX7D_PAD_SD3_DATA1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
104 MX7D_PAD_SD3_DATA2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
105 MX7D_PAD_SD3_DATA3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
106 MX7D_PAD_SD3_DATA4__SD3_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
107 MX7D_PAD_SD3_DATA5__SD3_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
108 MX7D_PAD_SD3_DATA6__SD3_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
109 MX7D_PAD_SD3_DATA7__SD3_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
110 MX7D_PAD_SD3_STROBE__SD3_STROBE
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
112 MX7D_PAD_SD3_RESET_B__GPIO6_IO11
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
115 static iomux_v3_cfg_t
const usb_otg1_pads
[] = {
116 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
),
119 static iomux_v3_cfg_t
const usb_otg2_pads
[] = {
120 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
),
123 #define IOX_SDI IMX_GPIO_NR(1, 9)
124 #define IOX_STCP IMX_GPIO_NR(1, 12)
125 #define IOX_SHCP IMX_GPIO_NR(1, 13)
127 static iomux_v3_cfg_t
const iox_pads
[] = {
129 MX7D_PAD_GPIO1_IO09__GPIO1_IO9
| MUX_PAD_CTRL(NO_PAD_CTRL
),
131 MX7D_PAD_GPIO1_IO12__GPIO1_IO12
| MUX_PAD_CTRL(NO_PAD_CTRL
),
133 MX7D_PAD_GPIO1_IO13__GPIO1_IO13
| MUX_PAD_CTRL(NO_PAD_CTRL
),
141 * SENSOR_RST_B --> Q4
168 static enum qn_level seq
[3][2] = {
169 {0, 1}, {1, 1}, {0, 0}
172 static enum qn_func qn_output
[8] = {
173 qn_disable
, qn_reset
, qn_reset
, qn_reset
, qn_reset
, qn_reset
, qn_enable
,
177 static void iox74lv_init(void)
181 for (i
= 7; i
>= 0; i
--) {
182 gpio_direction_output(IOX_SHCP
, 0);
183 gpio_direction_output(IOX_SDI
, seq
[qn_output
[i
]][0]);
185 gpio_direction_output(IOX_SHCP
, 1);
189 gpio_direction_output(IOX_STCP
, 0);
192 * shift register will be output to pins
194 gpio_direction_output(IOX_STCP
, 1);
196 for (i
= 7; i
>= 0; i
--) {
197 gpio_direction_output(IOX_SHCP
, 0);
198 gpio_direction_output(IOX_SDI
, seq
[qn_output
[i
]][1]);
200 gpio_direction_output(IOX_SHCP
, 1);
203 gpio_direction_output(IOX_STCP
, 0);
206 * shift register will be output to pins
208 gpio_direction_output(IOX_STCP
, 1);
211 #ifdef CONFIG_NAND_MXS
212 static iomux_v3_cfg_t
const gpmi_pads
[] = {
213 MX7D_PAD_SD3_DATA0__NAND_DATA00
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
214 MX7D_PAD_SD3_DATA1__NAND_DATA01
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
215 MX7D_PAD_SD3_DATA2__NAND_DATA02
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
216 MX7D_PAD_SD3_DATA3__NAND_DATA03
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
217 MX7D_PAD_SD3_DATA4__NAND_DATA04
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
218 MX7D_PAD_SD3_DATA5__NAND_DATA05
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
219 MX7D_PAD_SD3_DATA6__NAND_DATA06
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
220 MX7D_PAD_SD3_DATA7__NAND_DATA07
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
221 MX7D_PAD_SD3_CLK__NAND_CLE
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
222 MX7D_PAD_SD3_CMD__NAND_ALE
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
223 MX7D_PAD_SD3_STROBE__NAND_RE_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
224 MX7D_PAD_SD3_RESET_B__NAND_WE_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
225 MX7D_PAD_SAI1_MCLK__NAND_WP_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
226 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
227 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
228 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
229 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
230 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS
| MUX_PAD_CTRL(NAND_PAD_CTRL
),
231 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B
| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL
),
234 static void setup_gpmi_nand(void)
236 imx_iomux_v3_setup_multiple_pads(gpmi_pads
, ARRAY_SIZE(gpmi_pads
));
238 /* NAND_USDHC_BUS_CLK is set in rom */
243 #ifdef CONFIG_VIDEO_MXS
244 static iomux_v3_cfg_t
const lcd_pads
[] = {
245 MX7D_PAD_LCD_CLK__LCD_CLK
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
246 MX7D_PAD_LCD_ENABLE__LCD_ENABLE
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
247 MX7D_PAD_LCD_HSYNC__LCD_HSYNC
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
248 MX7D_PAD_LCD_VSYNC__LCD_VSYNC
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
249 MX7D_PAD_LCD_DATA00__LCD_DATA0
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
250 MX7D_PAD_LCD_DATA01__LCD_DATA1
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
251 MX7D_PAD_LCD_DATA02__LCD_DATA2
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
252 MX7D_PAD_LCD_DATA03__LCD_DATA3
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
253 MX7D_PAD_LCD_DATA04__LCD_DATA4
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
254 MX7D_PAD_LCD_DATA05__LCD_DATA5
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
255 MX7D_PAD_LCD_DATA06__LCD_DATA6
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
256 MX7D_PAD_LCD_DATA07__LCD_DATA7
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
257 MX7D_PAD_LCD_DATA08__LCD_DATA8
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
258 MX7D_PAD_LCD_DATA09__LCD_DATA9
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
259 MX7D_PAD_LCD_DATA10__LCD_DATA10
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
260 MX7D_PAD_LCD_DATA11__LCD_DATA11
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
261 MX7D_PAD_LCD_DATA12__LCD_DATA12
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
262 MX7D_PAD_LCD_DATA13__LCD_DATA13
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
263 MX7D_PAD_LCD_DATA14__LCD_DATA14
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
264 MX7D_PAD_LCD_DATA15__LCD_DATA15
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
265 MX7D_PAD_LCD_DATA16__LCD_DATA16
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
266 MX7D_PAD_LCD_DATA17__LCD_DATA17
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
267 MX7D_PAD_LCD_DATA18__LCD_DATA18
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
268 MX7D_PAD_LCD_DATA19__LCD_DATA19
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
269 MX7D_PAD_LCD_DATA20__LCD_DATA20
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
270 MX7D_PAD_LCD_DATA21__LCD_DATA21
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
271 MX7D_PAD_LCD_DATA22__LCD_DATA22
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
272 MX7D_PAD_LCD_DATA23__LCD_DATA23
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
274 MX7D_PAD_LCD_RESET__GPIO3_IO4
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
277 static iomux_v3_cfg_t
const pwm_pads
[] = {
278 /* Use GPIO for Brightness adjustment, duty cycle = period */
279 MX7D_PAD_GPIO1_IO01__GPIO1_IO1
| MUX_PAD_CTRL(NO_PAD_CTRL
),
282 static int setup_lcd(void)
284 imx_iomux_v3_setup_multiple_pads(lcd_pads
, ARRAY_SIZE(lcd_pads
));
286 imx_iomux_v3_setup_multiple_pads(pwm_pads
, ARRAY_SIZE(pwm_pads
));
289 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
291 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
293 /* Set Brightness to high */
294 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
300 #ifdef CONFIG_FEC_MXC
301 static iomux_v3_cfg_t
const fec1_pads
[] = {
302 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
303 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
304 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
305 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
306 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
307 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
308 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
309 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
310 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
311 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
312 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
313 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
314 MX7D_PAD_GPIO1_IO10__ENET1_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL_MII
),
315 MX7D_PAD_GPIO1_IO11__ENET1_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL_MII
),
318 static void setup_iomux_fec(void)
320 imx_iomux_v3_setup_multiple_pads(fec1_pads
, ARRAY_SIZE(fec1_pads
));
324 static void setup_iomux_uart(void)
326 imx_iomux_v3_setup_multiple_pads(uart1_pads
, ARRAY_SIZE(uart1_pads
));
329 #ifdef CONFIG_FSL_ESDHC
331 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
332 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
333 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
335 static struct fsl_esdhc_cfg usdhc_cfg
[3] = {
336 {USDHC1_BASE_ADDR
, 0, 4},
340 int board_mmc_get_env_dev(int devno
)
348 static int mmc_map_to_kernel_blk(int dev_no
)
356 int board_mmc_getcd(struct mmc
*mmc
)
358 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
361 switch (cfg
->esdhc_base
) {
362 case USDHC1_BASE_ADDR
:
363 ret
= !gpio_get_value(USDHC1_CD_GPIO
);
365 case USDHC3_BASE_ADDR
:
366 ret
= 1; /* Assume uSDHC3 emmc is always present */
373 int board_mmc_init(bd_t
*bis
)
377 * According to the board_mmc_init() the following map is done:
378 * (U-Boot device node) (Physical Port)
382 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
385 imx_iomux_v3_setup_multiple_pads(
386 usdhc1_pads
, ARRAY_SIZE(usdhc1_pads
));
387 gpio_request(USDHC1_CD_GPIO
, "usdhc1_cd");
388 gpio_direction_input(USDHC1_CD_GPIO
);
389 gpio_request(USDHC1_PWR_GPIO
, "usdhc1_pwr");
390 gpio_direction_output(USDHC1_PWR_GPIO
, 0);
392 gpio_direction_output(USDHC1_PWR_GPIO
, 1);
393 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
396 imx_iomux_v3_setup_multiple_pads(
397 usdhc3_emmc_pads
, ARRAY_SIZE(usdhc3_emmc_pads
));
398 gpio_request(USDHC3_PWR_GPIO
, "usdhc3_pwr");
399 gpio_direction_output(USDHC3_PWR_GPIO
, 0);
401 gpio_direction_output(USDHC3_PWR_GPIO
, 1);
402 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
405 printf("Warning: you configured more USDHC controllers"
406 "(%d) than supported by the board\n", i
+ 1);
410 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
418 static int check_mmc_autodetect(void)
420 char *autodetect_str
= getenv("mmcautodetect");
422 if ((autodetect_str
!= NULL
) &&
423 (strcmp(autodetect_str
, "yes") == 0)) {
430 static void mmc_late_init(void)
434 u32 dev_no
= mmc_get_env_dev();
436 if (!check_mmc_autodetect())
439 setenv_ulong("mmcdev", dev_no
);
442 sprintf(mmcblk
, "/dev/mmcblk%dp2 rootwait rw",
443 mmc_map_to_kernel_blk(dev_no
));
444 setenv("mmcroot", mmcblk
);
446 sprintf(cmd
, "mmc dev %d", dev_no
);
452 #ifdef CONFIG_FEC_MXC
453 int board_eth_init(bd_t
*bis
)
459 ret
= fecmxc_initialize_multi(bis
, 0,
460 CONFIG_FEC_MXC_PHYADDR
, IMX_FEC_BASE
);
462 printf("FEC1 MXC: %s:failed\n", __func__
);
467 static int setup_fec(void)
469 struct iomuxc_gpr_base_regs
*const iomuxc_gpr_regs
470 = (struct iomuxc_gpr_base_regs
*) IOMUXC_GPR_BASE_ADDR
;
472 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
473 clrsetbits_le32(&iomuxc_gpr_regs
->gpr
[1],
474 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK
|
475 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK
), 0);
477 return set_clk_enet(ENET_125MHz
);
481 int board_phy_config(struct phy_device
*phydev
)
483 /* enable rgmii rxc skew and phy mode select to RGMII copper */
484 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x21);
485 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1f, 0x7ea8);
486 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x2f);
487 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1f, 0x71b7);
489 if (phydev
->drv
->config
)
490 phydev
->drv
->config(phydev
);
495 #ifdef CONFIG_FSL_QSPI
496 static iomux_v3_cfg_t
const quadspi_pads
[] = {
497 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
498 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
499 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
500 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
501 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
502 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B
| MUX_PAD_CTRL(QSPI_PAD_CTRL
),
505 int board_qspi_init(void)
508 imx_iomux_v3_setup_multiple_pads(quadspi_pads
,
509 ARRAY_SIZE(quadspi_pads
));
518 int board_early_init_f(void)
522 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info1
);
523 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads
,
524 ARRAY_SIZE(usb_otg1_pads
));
525 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads
,
526 ARRAY_SIZE(usb_otg2_pads
));
533 /* address of boot parameters */
534 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
536 imx_iomux_v3_setup_multiple_pads(iox_pads
, ARRAY_SIZE(iox_pads
));
540 #ifdef CONFIG_FEC_MXC
544 #ifdef CONFIG_NAND_MXS
548 #ifdef CONFIG_VIDEO_MXS
552 #ifdef CONFIG_FSL_QSPI
561 int power_init_board(void)
565 unsigned int reg
, rev_id
;
567 ret
= power_pfuze3000_init(I2C_PMIC
);
571 p
= pmic_get("PFUZE3000");
576 pmic_reg_read(p
, PFUZE3000_DEVICEID
, ®
);
577 pmic_reg_read(p
, PFUZE3000_REVID
, &rev_id
);
578 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg
, rev_id
);
580 /* disable Low Power Mode during standby mode */
581 pmic_reg_read(p
, PFUZE3000_LDOGCTL
, ®
);
583 pmic_reg_write(p
, PFUZE3000_LDOGCTL
, reg
);
589 int board_late_init(void)
591 struct wdog_regs
*wdog
= (struct wdog_regs
*)WDOG1_BASE_ADDR
;
593 #ifdef CONFIG_ENV_IS_IN_MMC
597 imx_iomux_v3_setup_multiple_pads(wdog_pads
, ARRAY_SIZE(wdog_pads
));
599 set_wdog_reset(wdog
);
602 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
603 * since we use PMIC_PWRON to reset the board.
605 clrsetbits_le16(&wdog
->wcr
, 0, 0x10);
612 puts("Board: i.MX7D SABRESD\n");
617 #ifdef CONFIG_USB_EHCI_MX7
618 int board_usb_phy_mode(int port
)
621 return USB_INIT_DEVICE
;
623 return USB_INIT_HOST
;