2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/immap_85xx.h>
10 #include <asm/processor.h>
11 #include <asm/fsl_ddr_sdram.h>
12 #include <asm/fsl_ddr_dimm_params.h>
14 #include <asm/fsl_law.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 /* CONFIG_SYS_DDR_RAW_TIMING */
20 * Hynix H5TQ1G83TFR-H9C
22 dimm_params_t ddr_raw_timing
= {
24 .rank_density
= 536870912u,
25 .capacity
= 536870912u,
26 .primary_sdram_width
= 32,
32 .n_banks_per_sdram_device
= 8,
34 .burst_lengths_bitmask
= 0x0c,
37 .caslat_X
= 0x1e << 4, /* 5,6,7,8 */
48 .refresh_rate_ps
= 7800000,
52 int fsl_ddr_get_dimm_params(dimm_params_t
*pdimm
,
53 unsigned int controller_number
,
54 unsigned int dimm_number
)
56 const char dimm_model
[] = "Fixed DDR on board";
58 if ((controller_number
== 0) && (dimm_number
== 0)) {
59 memcpy(pdimm
, &ddr_raw_timing
, sizeof(dimm_params_t
));
60 memset(pdimm
->mpart
, 0, sizeof(pdimm
->mpart
));
61 memcpy(pdimm
->mpart
, dimm_model
, sizeof(dimm_model
) - 1);
67 void fsl_ddr_board_options(memctl_options_t
*popts
,
69 unsigned int ctrl_num
)
72 popts
->clk_adjust
= 6;
73 popts
->cpo_override
= 0x1f;
74 popts
->write_data_delay
= 2;
75 popts
->half_strength_driver_enable
= 1;
76 /* Write leveling override */
78 popts
->wrlvl_override
= 1;
79 popts
->wrlvl_sample
= 0xf;
80 popts
->wrlvl_start
= 0x8;
81 popts
->trwt_override
= 1;
84 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
85 popts
->cs_local_opts
[i
].odt_rd_cfg
= FSL_DDR_ODT_NEVER
;
86 popts
->cs_local_opts
[i
].odt_wr_cfg
= FSL_DDR_ODT_CS
;