2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
37 #include <asm/fsl_law.h>
41 #include "../common/ngpixis.h"
42 #include "../common/sgmii_riser.h"
44 DECLARE_GLOBAL_DATA_PTR
;
46 phys_size_t
fixed_sdram(void);
52 puts("Board: P2020DS ");
53 #ifdef CONFIG_PHYS_64BIT
54 puts("(36-bit addrmap) ");
57 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
58 in_8(&pixis
->id
), in_8(&pixis
->arch
), in_8(&pixis
->scver
));
60 sw
= in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH
));
61 sw
= (sw
& PIXIS_LBMAP_MASK
) >> PIXIS_LBMAP_SHIFT
;
64 /* The lower two bits are the actual vbank number */
65 printf("vBank: %d\n", sw
& 3);
72 phys_size_t
initdram(int board_type
)
74 phys_size_t dram_size
= 0;
76 puts("Initializing....");
79 dram_size
= fsl_ddr_sdram();
81 dram_size
= fixed_sdram();
83 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE
,
85 LAW_TRGT_IF_DDR
) < 0) {
86 printf("ERROR setting Local Access Windows for DDR\n");
90 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
91 dram_size
*= 0x100000;
97 #if !defined(CONFIG_DDR_SPD)
99 * Fixed sdram init -- doesn't use serial presence detect.
102 phys_size_t
fixed_sdram(void)
104 volatile ccsr_ddr_t
*ddr
= (ccsr_ddr_t
*)CONFIG_SYS_MPC85xx_DDR_ADDR
;
107 ddr
->cs0_config
= CONFIG_SYS_DDR_CS0_CONFIG
;
108 ddr
->timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
109 ddr
->timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
110 ddr
->sdram_mode
= CONFIG_SYS_DDR_MODE_1
;
111 ddr
->sdram_mode_2
= CONFIG_SYS_DDR_MODE_2
;
112 ddr
->sdram_md_cntl
= CONFIG_SYS_DDR_MODE_CTRL
;
113 ddr
->sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
114 ddr
->sdram_data_init
= CONFIG_SYS_DDR_DATA_INIT
;
115 ddr
->sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL
;
116 ddr
->sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL2
;
117 ddr
->ddr_zq_cntl
= CONFIG_SYS_DDR_ZQ_CNTL
;
118 ddr
->ddr_wrlvl_cntl
= CONFIG_SYS_DDR_WRLVL_CNTL
;
119 ddr
->ddr_cdr1
= CONFIG_SYS_DDR_CDR1
;
120 ddr
->timing_cfg_4
= CONFIG_SYS_DDR_TIMING_4
;
121 ddr
->timing_cfg_5
= CONFIG_SYS_DDR_TIMING_5
;
123 if (!strcmp("performance", getenv("perf_mode"))) {
124 /* Performance Mode Values */
126 ddr
->cs1_config
= CONFIG_SYS_DDR_CS1_CONFIG_PERF
;
127 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS_PERF
;
128 ddr
->cs1_bnds
= CONFIG_SYS_DDR_CS1_BNDS_PERF
;
129 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1_PERF
;
130 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2_PERF
;
136 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL_PERF
;
138 /* Stable Mode Values */
140 ddr
->cs1_config
= CONFIG_SYS_DDR_CS1_CONFIG
;
141 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS
;
142 ddr
->cs1_bnds
= CONFIG_SYS_DDR_CS1_BNDS
;
143 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
144 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
146 /* ECC will be assumed in stable mode */
147 ddr
->err_int_en
= CONFIG_SYS_DDR_ERR_INT_EN
;
148 ddr
->err_disable
= CONFIG_SYS_DDR_ERR_DIS
;
149 ddr
->err_sbe
= CONFIG_SYS_DDR_SBE
;
155 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
158 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
160 debug("DDR - 1st controller: memory initializing\n");
162 * Poll until memory is initialized.
163 * 512 Meg at 400 might hit this 200 times or so.
165 while ((ddr
->sdram_cfg_2
& (d_init
<< 4)) != 0)
167 debug("DDR: memory initialized\n\n");
172 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
178 static struct pci_controller pcie1_hose
;
182 static struct pci_controller pcie2_hose
;
186 static struct pci_controller pcie3_hose
;
190 void pci_init_board(void)
192 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
193 struct fsl_pci_info pci_info
[3];
194 u32 devdisr
, pordevsr
, io_sel
;
195 int first_free_busno
= 0;
198 int pcie_ep
, pcie_configured
;
200 devdisr
= in_be32(&gur
->devdisr
);
201 pordevsr
= in_be32(&gur
->pordevsr
);
202 io_sel
= (pordevsr
& MPC85xx_PORDEVSR_IO_SEL
) >> 19;
204 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr
, io_sel
);
206 if (!(pordevsr
& MPC85xx_PORDEVSR_SGMII2_DIS
))
207 printf("eTSEC2 is in sgmii mode.\n");
208 if (!(pordevsr
& MPC85xx_PORDEVSR_SGMII3_DIS
))
209 printf("eTSEC3 is in sgmii mode.\n");
213 pcie_configured
= is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2
, io_sel
);
215 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE2
)) {
216 SET_STD_PCIE_INFO(pci_info
[num
], 2);
217 pcie_ep
= fsl_setup_hose(&pcie2_hose
, pci_info
[num
].regs
);
218 printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
219 pcie_ep
? "Endpoint" : "Root Complex",
221 first_free_busno
= fsl_pci_init_port(&pci_info
[num
++],
222 &pcie2_hose
, first_free_busno
);
225 * The workaround doesn't work on p2020 because the location
226 * we try and read isn't valid on p2020, fix this later
230 * Activate ULI1575 legacy chip by performing a fake
231 * memory access. Needed to make ULI RTC work.
232 * Device 1d has the first on-board memory BAR.
235 pci_hose_read_config_dword(hose
, PCI_BDF(2, 0x1d, 0),
236 PCI_BASE_ADDRESS_1
, &temp32
);
237 if (temp32
>= CONFIG_SYS_PCIE3_MEM_BUS
) {
238 void *p
= pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
240 debug(" uli1575 read to %p\n", p
);
245 printf("PCIE2: disabled\n");
249 setbits_be32(&gur
->devdisr
, MPC85xx_DEVDISR_PCIE2
); /* disable */
253 pcie_configured
= is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3
, io_sel
);
255 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE3
)) {
256 SET_STD_PCIE_INFO(pci_info
[num
], 3);
257 pcie_ep
= fsl_setup_hose(&pcie3_hose
, pci_info
[num
].regs
);
258 printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
259 pcie_ep
? "Endpoint" : "Root Complex",
261 first_free_busno
= fsl_pci_init_port(&pci_info
[num
++],
262 &pcie3_hose
, first_free_busno
);
264 printf("PCIE3: disabled\n");
268 setbits_be32(&gur
->devdisr
, MPC85xx_DEVDISR_PCIE3
); /* disable */
272 pcie_configured
= is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1
, io_sel
);
274 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)) {
275 SET_STD_PCIE_INFO(pci_info
[num
], 1);
276 pcie_ep
= fsl_setup_hose(&pcie1_hose
, pci_info
[num
].regs
);
277 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
278 pcie_ep
? "Endpoint" : "Root Complex",
280 first_free_busno
= fsl_pci_init_port(&pci_info
[num
++],
281 &pcie1_hose
, first_free_busno
);
283 printf("PCIE1: disabled\n");
287 setbits_be32(&gur
->devdisr
, MPC85xx_DEVDISR_PCIE
); /* disable */
292 int board_early_init_r(void)
294 const unsigned int flashbase
= CONFIG_SYS_FLASH_BASE
;
295 const u8 flash_esel
= find_tlb_idx((void *)flashbase
, 1);
298 * Remap Boot flash + PROMJET region to caching-inhibited
299 * so that flash can be erased properly.
302 /* Flush d-cache and invalidate i-cache of any FLASH data */
306 /* invalidate existing TLB entry for flash + promjet */
307 disable_tlb(flash_esel
);
309 set_tlb(1, flashbase
, CONFIG_SYS_FLASH_BASE_PHYS
,
310 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
311 0, flash_esel
, BOOKE_PAGESZ_256M
, 1);
316 #ifdef CONFIG_TSEC_ENET
317 int board_eth_init(bd_t
*bis
)
319 struct tsec_info_struct tsec_info
[4];
320 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
324 SET_STD_TSEC_INFO(tsec_info
[num
], 1);
328 SET_STD_TSEC_INFO(tsec_info
[num
], 2);
329 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII2_DIS
))
330 tsec_info
[num
].flags
|= TSEC_SGMII
;
334 SET_STD_TSEC_INFO(tsec_info
[num
], 3);
335 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII3_DIS
))
336 tsec_info
[num
].flags
|= TSEC_SGMII
;
341 printf("No TSECs initialized\n");
346 #ifdef CONFIG_FSL_SGMII_RISER
347 fsl_sgmii_riser_init(tsec_info
, num
);
350 tsec_eth_init(bis
, tsec_info
, num
);
352 return pci_eth_init(bis
);
356 #if defined(CONFIG_OF_BOARD_SETUP)
357 void ft_board_setup(void *blob
, bd_t
*bd
)
362 ft_cpu_setup(blob
, bd
);
364 base
= getenv_bootm_low();
365 size
= getenv_bootm_size();
367 fdt_fixup_memory(blob
, (u64
)base
, (u64
)size
);
371 #ifdef CONFIG_FSL_SGMII_RISER
372 fsl_sgmii_riser_fdt_fixup(blob
);
378 void board_lmb_reserve(struct lmb
*lmb
)
380 cpu_mp_lmb_reserve(lmb
);