board/freescale/t4qds/t4240qds.c

   1 /*
   2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/cache.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_law.h>
  17 #include <asm/fsl_serdes.h>
  18 #include <asm/fsl_portals.h>
  19 #include <asm/fsl_liodn.h>
  20 #include <fm_eth.h>
  21
  22 #include "../common/qixis.h"
  23 #include "../common/vsc3316_3308.h"
  24 #include "t4qds.h"
  25 #include "t4240qds_qixis.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
  30                                 {8, 8}, {9, 9}, {14, 14}, {15, 15} };
  31
  32 static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
  33                                 {10, 10}, {11, 11}, {12, 12}, {13, 13} };
  34
  35 static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
  36                                 {10, 11}, {11, 10}, {12, 2}, {13, 3} };
  37
  38 static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
  39                                 {8, 9}, {9, 8}, {14, 1}, {15, 0} };
  40
  41 int checkboard(void)
  42 {
  43         char buf[64];
  44         u8 sw;
  45         struct cpu_type *cpu = gd->arch.cpu;
  46         unsigned int i;
  47
  48         printf("Board: %sQDS, ", cpu->name);
  49         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  50                QIXIS_READ(id), QIXIS_READ(arch));
  51
  52         sw = QIXIS_READ(brdcfg[0]);
  53         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  54
  55         if (sw < 0x8)
  56                 printf("vBank: %d\n", sw);
  57         else if (sw == 0x8)
  58                 puts("Promjet\n");
  59         else if (sw == 0x9)
  60                 puts("NAND\n");
  61         else
  62                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  63
  64         printf("FPGA: v%d (%s), build %d",
  65                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  66                (int)qixis_read_minor());
  67         /* the timestamp string contains "\n" at the end */
  68         printf(" on %s", qixis_read_time(buf));
  69
  70         /*
  71          * Display the actual SERDES reference clocks as configured by the
  72          * dip switches on the board.  Note that the SWx registers could
  73          * technically be set to force the reference clocks to match the
  74          * values that the SERDES expects (or vice versa).  For now, however,
  75          * we just display both values and hope the user notices when they
  76          * don't match.
  77          */
  78         puts("SERDES Reference Clocks: ");
  79         sw = QIXIS_READ(brdcfg[2]);
  80         for (i = 0; i < MAX_SERDES; i++) {
  81                 static const char * const freq[] = {
  82                         "100", "125", "156.25", "161.1328125"};
  83                 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  84
  85                 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
  86         }
  87         puts("\n");
  88
  89         return 0;
  90 }
  91
  92 int select_i2c_ch_pca9547(u8 ch)
  93 {
  94         int ret;
  95
  96         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  97         if (ret) {
  98                 puts("PCA: failed to select proper channel\n");
  99                 return ret;
 100         }
 101
 102         return 0;
 103 }
 104
 105 /*
 106  * read_voltage from sensor on I2C bus
 107  * We use average of 4 readings, waiting for 532us befor another reading
 108  */
 109 #define NUM_READINGS    4       /* prefer to be power of 2 for efficiency */
 110 #define WAIT_FOR_ADC    532     /* wait for 532 microseconds for ADC */
 111
 112 static inline int read_voltage(void)
 113 {
 114         int i, ret, voltage_read = 0;
 115         u16 vol_mon;
 116
 117         for (i = 0; i < NUM_READINGS; i++) {
 118                 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
 119                         I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
 120                 if (ret) {
 121                         printf("VID: failed to read core voltage\n");
 122                         return ret;
 123                 }
 124                 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
 125                         printf("VID: Core voltage sensor error\n");
 126                         return -1;
 127                 }
 128                 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
 129                 /* LSB = 4mv */
 130                 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
 131                 udelay(WAIT_FOR_ADC);
 132         }
 133         /* calculate the average */
 134         voltage_read /= NUM_READINGS;
 135
 136         return voltage_read;
 137 }
 138
 139 /*
 140  * We need to calculate how long before the voltage starts to drop or increase
 141  * It returns with the loop count. Each loop takes several readings (532us)
 142  */
 143 static inline int wait_for_voltage_change(int vdd_last)
 144 {
 145         int timeout, vdd_current;
 146
 147         vdd_current = read_voltage();
 148         /* wait until voltage starts to drop */
 149         for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
 150                 timeout < 100; timeout++) {
 151                 vdd_current = read_voltage();
 152         }
 153         if (timeout >= 100) {
 154                 printf("VID: Voltage adjustment timeout\n");
 155                 return -1;
 156         }
 157         return timeout;
 158 }
 159
 160 /*
 161  * argument 'wait' is the time we know the voltage difference can be measured
 162  * this function keeps reading the voltage until it is stable
 163  */
 164 static inline int wait_for_voltage_stable(int wait)
 165 {
 166         int timeout, vdd_current, vdd_last;
 167
 168         vdd_last = read_voltage();
 169         udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
 170         /* wait until voltage is stable */
 171         vdd_current = read_voltage();
 172         for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
 173                 timeout < 100; timeout++) {
 174                 vdd_last = vdd_current;
 175                 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
 176                 vdd_current = read_voltage();
 177         }
 178         if (timeout >= 100) {
 179                 printf("VID: Voltage adjustment timeout\n");
 180                 return -1;
 181         }
 182
 183         return vdd_current;
 184 }
 185
 186 static inline int set_voltage(u8 vid)
 187 {
 188         int wait, vdd_last;
 189
 190         vdd_last = read_voltage();
 191         QIXIS_WRITE(brdcfg[6], vid);
 192         wait = wait_for_voltage_change(vdd_last);
 193         if (wait < 0)
 194                 return -1;
 195         debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
 196         wait = wait ? wait : 1;
 197
 198         vdd_last = wait_for_voltage_stable(wait);
 199         if (vdd_last < 0)
 200                 return -1;
 201         debug("VID: Current voltage is %d mV\n", vdd_last);
 202
 203         return vdd_last;
 204 }
 205
 206
 207 static int adjust_vdd(ulong vdd_override)
 208 {
 209         int re_enable = disable_interrupts();
 210         ccsr_gur_t __iomem *gur =
 211                 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 212         u32 fusesr;
 213         u8 vid, vid_current;
 214         int vdd_target, vdd_current, vdd_last;
 215         int ret;
 216         unsigned long vdd_string_override;
 217         char *vdd_string;
 218         static const uint16_t vdd[32] = {
 219                 0,      /* unused */
 220                 9875,   /* 0.9875V */
 221                 9750,
 222                 9625,
 223                 9500,
 224                 9375,
 225                 9250,
 226                 9125,
 227                 9000,
 228                 8875,
 229                 8750,
 230                 8625,
 231                 8500,
 232                 8375,
 233                 8250,
 234                 8125,
 235                 10000,  /* 1.0000V */
 236                 10125,
 237                 10250,
 238                 10375,
 239                 10500,
 240                 10625,
 241                 10750,
 242                 10875,
 243                 11000,
 244                 0,      /* reserved */
 245         };
 246         struct vdd_drive {
 247                 u8 vid;
 248                 unsigned voltage;
 249         };
 250
 251         ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
 252         if (ret) {
 253                 debug("VID: I2c failed to switch channel\n");
 254                 ret = -1;
 255                 goto exit;
 256         }
 257
 258         /* get the voltage ID from fuse status register */
 259         fusesr = in_be32(&gur->dcfg_fusesr);
 260         vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
 261                 FSL_CORENET_DCFG_FUSESR_VID_MASK;
 262         if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
 263                 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
 264                         FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
 265         }
 266         vdd_target = vdd[vid];
 267
 268         /* check override variable for overriding VDD */
 269         vdd_string = getenv("t4240qds_vdd_mv");
 270         if (vdd_override == 0 && vdd_string &&
 271             !strict_strtoul(vdd_string, 10, &vdd_string_override))
 272                 vdd_override = vdd_string_override;
 273         if (vdd_override >= 819 && vdd_override <= 1212) {
 274                 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
 275                 debug("VDD override is %lu\n", vdd_override);
 276         } else if (vdd_override != 0) {
 277                 printf("Invalid value.\n");
 278         }
 279
 280         if (vdd_target == 0) {
 281                 debug("VID: VID not used\n");
 282                 ret = 0;
 283                 goto exit;
 284         } else {
 285                 /* round up and divice by 10 to get a value in mV */
 286                 vdd_target = DIV_ROUND_UP(vdd_target, 10);
 287                 debug("VID: vid = %d mV\n", vdd_target);
 288         }
 289
 290         /*
 291          * Check current board VID setting
 292          * Voltage regulator support output to 6.250mv step
 293          * The highes voltage allowed for this board is (vid=0x40) 1.21250V
 294          * the lowest is (vid=0x7f) 0.81875V
 295          */
 296         vid_current =  QIXIS_READ(brdcfg[6]);
 297         vdd_current = 121250 - (vid_current - 0x40) * 625;
 298         debug("VID: Current vid setting is (0x%x) %d mV\n",
 299               vid_current, vdd_current/100);
 300
 301         /*
 302          * Read voltage monitor to check real voltage.
 303          * Voltage monitor LSB is 4mv.
 304          */
 305         vdd_last = read_voltage();
 306         if (vdd_last < 0) {
 307                 printf("VID: Could not read voltage sensor abort VID adjustment\n");
 308                 ret = -1;
 309                 goto exit;
 310         }
 311         debug("VID: Core voltage is at %d mV\n", vdd_last);
 312         /*
 313          * Adjust voltage to at or 8mV above target.
 314          * Each step of adjustment is 6.25mV.
 315          * Stepping down too fast may cause over current.
 316          */
 317         while (vdd_last > 0 && vid_current < 0x80 &&
 318                 vdd_last > (vdd_target + 8)) {
 319                 vid_current++;
 320                 vdd_last = set_voltage(vid_current);
 321         }
 322         /*
 323          * Check if we need to step up
 324          * This happens when board voltage switch was set too low
 325          */
 326         while (vdd_last > 0 && vid_current >= 0x40 &&
 327                 vdd_last < vdd_target + 2) {
 328                 vid_current--;
 329                 vdd_last = set_voltage(vid_current);
 330         }
 331         if (vdd_last > 0)
 332                 printf("VID: Core voltage %d mV\n", vdd_last);
 333         else
 334                 ret = -1;
 335
 336 exit:
 337         if (re_enable)
 338                 enable_interrupts();
 339         return ret;
 340 }
 341
 342 /* Configure Crossbar switches for Front-Side SerDes Ports */
 343 int config_frontside_crossbar_vsc3316(void)
 344 {
 345         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 346         u32 srds_prtcl_s1, srds_prtcl_s2;
 347         int ret;
 348
 349         ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
 350         if (ret)
 351                 return ret;
 352
 353         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 354                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 355         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 356         switch (srds_prtcl_s1) {
 357         case 38:
 358                 /* swap first lane and third lane on slot1 */
 359                 vsc3316_fsm1_tx[0][1] = 14;
 360                 vsc3316_fsm1_tx[6][1] = 0;
 361                 vsc3316_fsm1_rx[1][1] = 2;
 362                 vsc3316_fsm1_rx[6][1] = 13;
 363         case 40:
 364         case 46:
 365         case 48:
 366                 /* swap first lane and third lane on slot2 */
 367                 vsc3316_fsm1_tx[2][1] = 8;
 368                 vsc3316_fsm1_tx[4][1] = 6;
 369                 vsc3316_fsm1_rx[2][1] = 10;
 370                 vsc3316_fsm1_rx[5][1] = 5;
 371         default:
 372                 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
 373                 if (ret)
 374                         return ret;
 375                 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
 376                 if (ret)
 377                         return ret;
 378                 break;
 379         }
 380
 381         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 382                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 383         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 384         switch (srds_prtcl_s2) {
 385         case 38:
 386                 /* swap first lane and third lane on slot3 */
 387                 vsc3316_fsm2_tx[2][1] = 11;
 388                 vsc3316_fsm2_tx[5][1] = 4;
 389                 vsc3316_fsm2_rx[2][1] = 9;
 390                 vsc3316_fsm2_rx[4][1] = 7;
 391         case 40:
 392         case 46:
 393         case 48:
 394         case 50:
 395         case 52:
 396         case 54:
 397                 /* swap first lane and third lane on slot4 */
 398                 vsc3316_fsm2_tx[6][1] = 3;
 399                 vsc3316_fsm2_tx[1][1] = 12;
 400                 vsc3316_fsm2_rx[0][1] = 1;
 401                 vsc3316_fsm2_rx[6][1] = 15;
 402         default:
 403                 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
 404                 if (ret)
 405                         return ret;
 406                 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
 407                 if (ret)
 408                         return ret;
 409                 break;
 410         }
 411
 412         return 0;
 413 }
 414
 415 int config_backside_crossbar_mux(void)
 416 {
 417         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 418         u32 srds_prtcl_s3, srds_prtcl_s4;
 419         u8 brdcfg;
 420
 421         srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
 422                         FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
 423         srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
 424         switch (srds_prtcl_s3) {
 425         case 0:
 426                 /* SerDes3 is not enabled */
 427                 break;
 428         case 2:
 429         case 9:
 430         case 10:
 431                 /* SD3(0:7) => SLOT5(0:7) */
 432                 brdcfg = QIXIS_READ(brdcfg[12]);
 433                 brdcfg &= ~BRDCFG12_SD3MX_MASK;
 434                 brdcfg |= BRDCFG12_SD3MX_SLOT5;
 435                 QIXIS_WRITE(brdcfg[12], brdcfg);
 436                 break;
 437         case 4:
 438         case 6:
 439         case 8:
 440         case 12:
 441         case 14:
 442         case 16:
 443         case 17:
 444         case 19:
 445         case 20:
 446                 /* SD3(4:7) => SLOT6(0:3) */
 447                 brdcfg = QIXIS_READ(brdcfg[12]);
 448                 brdcfg &= ~BRDCFG12_SD3MX_MASK;
 449                 brdcfg |= BRDCFG12_SD3MX_SLOT6;
 450                 QIXIS_WRITE(brdcfg[12], brdcfg);
 451                 break;
 452         default:
 453                 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
 454                        srds_prtcl_s3);
 455                 return -1;
 456         }
 457
 458         srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
 459                         FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
 460         srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
 461         switch (srds_prtcl_s4) {
 462         case 0:
 463                 /* SerDes4 is not enabled */
 464                 break;
 465         case 2:
 466                 /* 10b, SD4(0:7) => SLOT7(0:7) */
 467                 brdcfg = QIXIS_READ(brdcfg[12]);
 468                 brdcfg &= ~BRDCFG12_SD4MX_MASK;
 469                 brdcfg |= BRDCFG12_SD4MX_SLOT7;
 470                 QIXIS_WRITE(brdcfg[12], brdcfg);
 471                 break;
 472         case 4:
 473         case 6:
 474         case 8:
 475                 /* x1b, SD4(4:7) => SLOT8(0:3) */
 476                 brdcfg = QIXIS_READ(brdcfg[12]);
 477                 brdcfg &= ~BRDCFG12_SD4MX_MASK;
 478                 brdcfg |= BRDCFG12_SD4MX_SLOT8;
 479                 QIXIS_WRITE(brdcfg[12], brdcfg);
 480                 break;
 481         case 10:
 482         case 12:
 483         case 14:
 484         case 16:
 485         case 18:
 486                 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
 487                 brdcfg = QIXIS_READ(brdcfg[12]);
 488                 brdcfg &= ~BRDCFG12_SD4MX_MASK;
 489                 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
 490                 QIXIS_WRITE(brdcfg[12], brdcfg);
 491                 break;
 492         default:
 493                 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
 494                        srds_prtcl_s4);
 495                 return -1;
 496         }
 497
 498         return 0;
 499 }
 500
 501 int board_early_init_r(void)
 502 {
 503         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 504         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 505
 506         /*
 507          * Remap Boot flash + PROMJET region to caching-inhibited
 508          * so that flash can be erased properly.
 509          */
 510
 511         /* Flush d-cache and invalidate i-cache of any FLASH data */
 512         flush_dcache();
 513         invalidate_icache();
 514
 515         /* invalidate existing TLB entry for flash + promjet */
 516         disable_tlb(flash_esel);
 517
 518         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 519                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 520                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 521
 522         set_liodns();
 523 #ifdef CONFIG_SYS_DPAA_QBMAN
 524         setup_portals();
 525 #endif
 526
 527         /* Disable remote I2C connection to qixis fpga */
 528         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 529
 530         /*
 531          * Adjust core voltage according to voltage ID
 532          * This function changes I2C mux to channel 2.
 533          */
 534         if (adjust_vdd(0))
 535                 printf("Warning: Adjusting core voltage failed.\n");
 536
 537         /* Configure board SERDES ports crossbar */
 538         config_frontside_crossbar_vsc3316();
 539         config_backside_crossbar_mux();
 540         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 541
 542         return 0;
 543 }
 544
 545 unsigned long get_board_sys_clk(void)
 546 {
 547         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 548 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 549         /* use accurate clock measurement */
 550         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 551         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 552         u32 val;
 553
 554         val =  freq * base;
 555         if (val) {
 556                 debug("SYS Clock measurement is: %d\n", val);
 557                 return val;
 558         } else {
 559                 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
 560         }
 561 #endif
 562
 563         switch (sysclk_conf & 0x0F) {
 564         case QIXIS_SYSCLK_83:
 565                 return 83333333;
 566         case QIXIS_SYSCLK_100:
 567                 return 100000000;
 568         case QIXIS_SYSCLK_125:
 569                 return 125000000;
 570         case QIXIS_SYSCLK_133:
 571                 return 133333333;
 572         case QIXIS_SYSCLK_150:
 573                 return 150000000;
 574         case QIXIS_SYSCLK_160:
 575                 return 160000000;
 576         case QIXIS_SYSCLK_166:
 577                 return 166666666;
 578         }
 579         return 66666666;
 580 }
 581
 582 unsigned long get_board_ddr_clk(void)
 583 {
 584         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 585 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 586         /* use accurate clock measurement */
 587         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 588         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 589         u32 val;
 590
 591         val =  freq * base;
 592         if (val) {
 593                 debug("DDR Clock measurement is: %d\n", val);
 594                 return val;
 595         } else {
 596                 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
 597         }
 598 #endif
 599
 600         switch ((ddrclk_conf & 0x30) >> 4) {
 601         case QIXIS_DDRCLK_100:
 602                 return 100000000;
 603         case QIXIS_DDRCLK_125:
 604                 return 125000000;
 605         case QIXIS_DDRCLK_133:
 606                 return 133333333;
 607         }
 608         return 66666666;
 609 }
 610
 611 static const char *serdes_clock_to_string(u32 clock)
 612 {
 613         switch (clock) {
 614         case SRDS_PLLCR0_RFCK_SEL_100:
 615                 return "100";
 616         case SRDS_PLLCR0_RFCK_SEL_125:
 617                 return "125";
 618         case SRDS_PLLCR0_RFCK_SEL_156_25:
 619                 return "156.25";
 620         case SRDS_PLLCR0_RFCK_SEL_161_13:
 621                 return "161.1328125";
 622         default:
 623                 return "???";
 624         }
 625 }
 626
 627 int misc_init_r(void)
 628 {
 629         u8 sw;
 630         serdes_corenet_t *srds_regs =
 631                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 632         u32 actual[MAX_SERDES];
 633         unsigned int i;
 634
 635         sw = QIXIS_READ(brdcfg[2]);
 636         for (i = 0; i < MAX_SERDES; i++) {
 637                 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
 638                 switch (clock) {
 639                 case 0:
 640                         actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
 641                         break;
 642                 case 1:
 643                         actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
 644                         break;
 645                 case 2:
 646                         actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
 647                         break;
 648                 case 3:
 649                         actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
 650                         break;
 651                 }
 652         }
 653
 654         for (i = 0; i < MAX_SERDES; i++) {
 655                 u32 pllcr0 = srds_regs->bank[i].pllcr0;
 656                 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
 657                 if (expected != actual[i]) {
 658                         printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
 659                                i + 1, serdes_clock_to_string(expected),
 660                                serdes_clock_to_string(actual[i]));
 661                 }
 662         }
 663
 664         return 0;
 665 }
 666
 667 void ft_board_setup(void *blob, bd_t *bd)
 668 {
 669         phys_addr_t base;
 670         phys_size_t size;
 671
 672         ft_cpu_setup(blob, bd);
 673
 674         base = getenv_bootm_low();
 675         size = getenv_bootm_size();
 676
 677         fdt_fixup_memory(blob, (u64)base, (u64)size);
 678
 679 #ifdef CONFIG_PCI
 680         pci_of_setup(blob, bd);
 681 #endif
 682
 683         fdt_fixup_liodn(blob);
 684         fdt_fixup_dr_usb(blob, bd);
 685
 686 #ifdef CONFIG_SYS_DPAA_FMAN
 687         fdt_fixup_fman_ethernet(blob);
 688         fdt_fixup_board_enet(blob);
 689 #endif
 690 }
 691
 692 /*
 693  * This function is called by bdinfo to print detail board information.
 694  * As an exmaple for future board, we organize the messages into
 695  * several sections. If applicable, the message is in the format of
 696  * <name>      = <value>
 697  * It should aligned with normal output of bdinfo command.
 698  *
 699  * Voltage: Core, DDR and another configurable voltages
 700  * Clock  : Critical clocks which are not printed already
 701  * RCW    : RCW source if not printed already
 702  * Misc   : Other important information not in above catagories
 703  */
 704 void board_detail(void)
 705 {
 706         int i;
 707         u8 brdcfg[16], dutcfg[16], rst_ctl;
 708         int vdd, rcwsrc;
 709         static const char * const clk[] = {"66.67", "100", "125", "133.33"};
 710
 711         for (i = 0; i < 16; i++) {
 712                 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
 713                 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
 714         }
 715
 716         /* Voltage secion */
 717         if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
 718                 vdd = read_voltage();
 719                 if (vdd > 0)
 720                         printf("Core voltage= %d mV\n", vdd);
 721                 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 722         }
 723
 724         printf("XVDD        = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
 725
 726         /* clock section */
 727         printf("SYSCLK      = %s MHz\nDDRCLK      = %s MHz\n",
 728                clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
 729
 730         /* RCW section */
 731         rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
 732         puts("RCW source  = ");
 733         switch (rcwsrc) {
 734         case 0x017:
 735         case 0x01f:
 736                 puts("8-bit NOR\n");
 737                 break;
 738         case 0x027:
 739         case 0x02F:
 740                 puts("16-bit NOR\n");
 741                 break;
 742         case 0x040:
 743                 puts("SDHC/eMMC\n");
 744                 break;
 745         case 0x044:
 746                 puts("SPI 16-bit addressing\n");
 747                 break;
 748         case 0x045:
 749                 puts("SPI 24-bit addressing\n");
 750                 break;
 751         case 0x048:
 752                 puts("I2C normal addressing\n");
 753                 break;
 754         case 0x049:
 755                 puts("I2C extended addressing\n");
 756                 break;
 757         case 0x108:
 758         case 0x109:
 759         case 0x10a:
 760         case 0x10b:
 761                 puts("8-bit NAND, 2KB\n");
 762                 break;
 763         default:
 764                 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
 765                         puts("Hard-coded RCW\n");
 766                 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
 767                         puts("8-bit NAND, 4KB\n");
 768                 else
 769                         puts("unknown\n");
 770                 break;
 771         }
 772
 773         /* Misc section */
 774         rst_ctl = QIXIS_READ(rst_ctl);
 775         puts("HRESET_REQ  = ");
 776         switch (rst_ctl & 0x30) {
 777         case 0x00:
 778                 puts("Ignored\n");
 779                 break;
 780         case 0x10:
 781                 puts("Assert HRESET\n");
 782                 break;
 783         case 0x30:
 784                 puts("Reset system\n");
 785                 break;
 786         default:
 787                 puts("N/A\n");
 788                 break;
 789         }
 790 }
 791
 792 /*
 793  * Reverse engineering switch settings.
 794  * Some bits cannot be figured out. They will be displayed as
 795  * underscore in binary format. mask[] has those bits.
 796  * Some bits are calculated differently than the actual switches
 797  * if booting with overriding by FPGA.
 798  */
 799 void qixis_dump_switch(void)
 800 {
 801         int i;
 802         u8 sw[9];
 803
 804         /*
 805          * Any bit with 1 means that bit cannot be reverse engineered.
 806          * It will be displayed as _ in binary format.
 807          */
 808         static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
 809         char buf[10];
 810         u8 brdcfg[16], dutcfg[16];
 811
 812         for (i = 0; i < 16; i++) {
 813                 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
 814                 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
 815         }
 816
 817         sw[0] = dutcfg[0];
 818         sw[1] = (dutcfg[1] << 0x07)             |
 819                 ((dutcfg[12] & 0xC0) >> 1)      |
 820                 ((dutcfg[11] & 0xE0) >> 3)      |
 821                 ((dutcfg[6] & 0x80) >> 6)       |
 822                 ((dutcfg[1] & 0x80) >> 7);
 823         sw[2] = ((brdcfg[1] & 0x0f) << 4)       |
 824                 ((brdcfg[1] & 0x30) >> 2)       |
 825                 ((brdcfg[1] & 0x40) >> 5)       |
 826                 ((brdcfg[1] & 0x80) >> 7);
 827         sw[3] = brdcfg[2];
 828         sw[4] = ((dutcfg[2] & 0x01) << 7)       |
 829                 ((dutcfg[2] & 0x06) << 4)       |
 830                 ((~QIXIS_READ(present)) & 0x10) |
 831                 ((brdcfg[3] & 0x80) >> 4)       |
 832                 ((brdcfg[3] & 0x01) << 2)       |
 833                 ((brdcfg[6] == 0x62) ? 3 :
 834                 ((brdcfg[6] == 0x5a) ? 2 :
 835                 ((brdcfg[6] == 0x5e) ? 1 : 0)));
 836         sw[5] = ((brdcfg[0] & 0x0f) << 4)       |
 837                 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
 838                 ((brdcfg[0] & 0x40) >> 5);
 839         sw[6] = (brdcfg[11] & 0x20)             |
 840                 ((brdcfg[5] & 0x02) << 3);
 841         sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
 842                 ((brdcfg[5] & 0x10) << 2);
 843         sw[8] = ((brdcfg[12] & 0x08) << 4)      |
 844                 ((brdcfg[12] & 0x03) << 5);
 845
 846         puts("DIP switch (reverse-engineering)\n");
 847         for (i = 0; i < 9; i++) {
 848                 printf("SW%d         = 0b%s (0x%02x)\n",
 849                        i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
 850         }
 851 }
 852
 853 static int do_vdd_adjust(cmd_tbl_t *cmdtp,
 854                          int flag, int argc,
 855                          char * const argv[])
 856 {
 857         ulong override;
 858
 859         if (argc < 2)
 860                 return CMD_RET_USAGE;
 861         if (!strict_strtoul(argv[1], 10, &override))
 862                 adjust_vdd(override);   /* the value is checked by callee */
 863         else
 864                 return CMD_RET_USAGE;
 865
 866         return 0;
 867 }
 868
 869 U_BOOT_CMD(
 870         vdd_override, 2, 0, do_vdd_adjust,
 871         "Override VDD",
 872         "- override with the voltage specified in mV, eg. 1050"
 873 );