2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/mx6-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/imx-common/mxc_i2c.h>
14 #include <power/pmic.h>
15 #include <power/ltc3676_pmic.h>
16 #include <power/pfuze100_pmic.h>
20 /* UART1: Function varies per baseboard */
21 static iomux_v3_cfg_t
const uart1_pads
[] = {
22 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
23 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
26 /* UART2: Serial Console */
27 static iomux_v3_cfg_t
const uart2_pads
[] = {
28 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
29 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
32 void setup_iomux_uart(void)
34 SETUP_IOMUX_PADS(uart1_pads
);
35 SETUP_IOMUX_PADS(uart2_pads
);
39 static struct i2c_pads_info mx6q_i2c_pad_info0
= {
41 .i2c_mode
= MX6Q_PAD_EIM_D21__I2C1_SCL
| PC
,
42 .gpio_mode
= MX6Q_PAD_EIM_D21__GPIO3_IO21
| PC
,
43 .gp
= IMX_GPIO_NR(3, 21)
46 .i2c_mode
= MX6Q_PAD_EIM_D28__I2C1_SDA
| PC
,
47 .gpio_mode
= MX6Q_PAD_EIM_D28__GPIO3_IO28
| PC
,
48 .gp
= IMX_GPIO_NR(3, 28)
51 static struct i2c_pads_info mx6dl_i2c_pad_info0
= {
53 .i2c_mode
= MX6DL_PAD_EIM_D21__I2C1_SCL
| PC
,
54 .gpio_mode
= MX6DL_PAD_EIM_D21__GPIO3_IO21
| PC
,
55 .gp
= IMX_GPIO_NR(3, 21)
58 .i2c_mode
= MX6DL_PAD_EIM_D28__I2C1_SDA
| PC
,
59 .gpio_mode
= MX6DL_PAD_EIM_D28__GPIO3_IO28
| PC
,
60 .gp
= IMX_GPIO_NR(3, 28)
64 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
65 static struct i2c_pads_info mx6q_i2c_pad_info1
= {
67 .i2c_mode
= MX6Q_PAD_KEY_COL3__I2C2_SCL
| PC
,
68 .gpio_mode
= MX6Q_PAD_KEY_COL3__GPIO4_IO12
| PC
,
69 .gp
= IMX_GPIO_NR(4, 12)
72 .i2c_mode
= MX6Q_PAD_KEY_ROW3__I2C2_SDA
| PC
,
73 .gpio_mode
= MX6Q_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
74 .gp
= IMX_GPIO_NR(4, 13)
77 static struct i2c_pads_info mx6dl_i2c_pad_info1
= {
79 .i2c_mode
= MX6DL_PAD_KEY_COL3__I2C2_SCL
| PC
,
80 .gpio_mode
= MX6DL_PAD_KEY_COL3__GPIO4_IO12
| PC
,
81 .gp
= IMX_GPIO_NR(4, 12)
84 .i2c_mode
= MX6DL_PAD_KEY_ROW3__I2C2_SDA
| PC
,
85 .gpio_mode
= MX6DL_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
86 .gp
= IMX_GPIO_NR(4, 13)
90 /* I2C3: Misc/Expansion */
91 static struct i2c_pads_info mx6q_i2c_pad_info2
= {
93 .i2c_mode
= MX6Q_PAD_GPIO_3__I2C3_SCL
| PC
,
94 .gpio_mode
= MX6Q_PAD_GPIO_3__GPIO1_IO03
| PC
,
95 .gp
= IMX_GPIO_NR(1, 3)
98 .i2c_mode
= MX6Q_PAD_GPIO_6__I2C3_SDA
| PC
,
99 .gpio_mode
= MX6Q_PAD_GPIO_6__GPIO1_IO06
| PC
,
100 .gp
= IMX_GPIO_NR(1, 6)
103 static struct i2c_pads_info mx6dl_i2c_pad_info2
= {
105 .i2c_mode
= MX6DL_PAD_GPIO_3__I2C3_SCL
| PC
,
106 .gpio_mode
= MX6DL_PAD_GPIO_3__GPIO1_IO03
| PC
,
107 .gp
= IMX_GPIO_NR(1, 3)
110 .i2c_mode
= MX6DL_PAD_GPIO_6__I2C3_SDA
| PC
,
111 .gpio_mode
= MX6DL_PAD_GPIO_6__GPIO1_IO06
| PC
,
112 .gp
= IMX_GPIO_NR(1, 6)
116 void setup_ventana_i2c(void)
118 if (is_cpu_type(MXC_CPU_MX6Q
)) {
119 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info0
);
120 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info1
);
121 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info2
);
123 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info0
);
124 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info1
);
125 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info2
);
130 * Baseboard specific GPIO
133 /* common to add baseboards */
134 static iomux_v3_cfg_t
const gw_gpio_pads
[] = {
136 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| DIO_PAD_CFG
),
138 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14
| DIO_PAD_CFG
),
142 static iomux_v3_cfg_t
const gwproto_gpio_pads
[] = {
144 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
146 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
148 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
150 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| DIO_PAD_CFG
),
152 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
154 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
156 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
158 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| DIO_PAD_CFG
),
160 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
| DIO_PAD_CFG
),
162 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
165 static iomux_v3_cfg_t
const gw51xx_gpio_pads
[] = {
167 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
169 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
171 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
173 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
176 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
178 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20
| DIO_PAD_CFG
),
180 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| DIO_PAD_CFG
),
182 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
185 static iomux_v3_cfg_t
const gw52xx_gpio_pads
[] = {
187 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| DIO_PAD_CFG
),
189 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
191 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
193 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
195 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
197 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
199 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
201 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27
| DIO_PAD_CFG
),
203 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
205 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
207 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
208 /* PCI_RST# (GW522x) */
209 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23
| DIO_PAD_CFG
),
211 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| DIO_PAD_CFG
),
213 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
216 static iomux_v3_cfg_t
const gw53xx_gpio_pads
[] = {
218 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| DIO_PAD_CFG
),
220 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
222 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
224 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
226 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
228 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
230 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
232 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
234 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| DIO_PAD_CFG
),
236 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27
| DIO_PAD_CFG
),
238 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
240 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
242 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| DIO_PAD_CFG
),
244 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
247 static iomux_v3_cfg_t
const gw54xx_gpio_pads
[] = {
249 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| DIO_PAD_CFG
),
251 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
253 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
255 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
257 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
259 IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
| DIO_PAD_CFG
),
261 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21
| DIO_PAD_CFG
),
263 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24
| DIO_PAD_CFG
),
265 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| DIO_PAD_CFG
),
267 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(IRQ_PAD_CTRL
)),
269 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| DIO_PAD_CFG
),
271 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
273 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| DIO_PAD_CFG
),
275 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| DIO_PAD_CFG
),
277 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17
| DIO_PAD_CFG
),
280 static iomux_v3_cfg_t
const gw551x_gpio_pads
[] = {
282 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
284 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
286 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| DIO_PAD_CFG
),
288 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
291 static iomux_v3_cfg_t
const gw552x_gpio_pads
[] = {
293 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| DIO_PAD_CFG
),
295 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07
| DIO_PAD_CFG
),
297 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
| DIO_PAD_CFG
),
299 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| DIO_PAD_CFG
),
301 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| DIO_PAD_CFG
),
303 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| DIO_PAD_CFG
),
305 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| DIO_PAD_CFG
),
307 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18
| DIO_PAD_CFG
),
308 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20
| DIO_PAD_CFG
),
309 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21
| DIO_PAD_CFG
),
310 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22
| DIO_PAD_CFG
),
311 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23
| DIO_PAD_CFG
),
312 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25
| DIO_PAD_CFG
),
314 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01
| DIO_PAD_CFG
),
316 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| DIO_PAD_CFG
),
318 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
321 static iomux_v3_cfg_t
const gw553x_gpio_pads
[] = {
323 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10
| DIO_PAD_CFG
),
325 IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11
| DIO_PAD_CFG
),
328 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20
| DIO_PAD_CFG
),
330 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| DIO_PAD_CFG
),
332 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| DIO_PAD_CFG
),
337 * Board Specific GPIO
339 struct ventana gpio_cfg
[GW_UNKNOWN
] = {
342 .gpio_pads
= gw54xx_gpio_pads
,
343 .num_pads
= ARRAY_SIZE(gw54xx_gpio_pads
)/2,
346 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
) },
348 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT
) },
352 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
354 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
358 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09
) },
360 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT
) },
364 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10
) },
366 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT
) },
376 .pcie_rst
= IMX_GPIO_NR(1, 29),
377 .mezz_pwren
= IMX_GPIO_NR(4, 7),
378 .mezz_irq
= IMX_GPIO_NR(4, 9),
379 .rs485en
= IMX_GPIO_NR(3, 24),
380 .dioi2c_en
= IMX_GPIO_NR(4, 5),
381 .pcie_sson
= IMX_GPIO_NR(1, 20),
386 .gpio_pads
= gw51xx_gpio_pads
,
387 .num_pads
= ARRAY_SIZE(gw51xx_gpio_pads
)/2,
390 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
396 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
398 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
402 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
404 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
408 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18
) },
410 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT
) },
419 .pcie_rst
= IMX_GPIO_NR(1, 0),
420 .mezz_pwren
= IMX_GPIO_NR(2, 19),
421 .mezz_irq
= IMX_GPIO_NR(2, 18),
422 .gps_shdn
= IMX_GPIO_NR(1, 2),
423 .vidin_en
= IMX_GPIO_NR(5, 20),
424 .wdis
= IMX_GPIO_NR(7, 12),
429 .gpio_pads
= gw52xx_gpio_pads
,
430 .num_pads
= ARRAY_SIZE(gw52xx_gpio_pads
)/2,
433 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
439 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
441 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
445 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
447 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
451 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
463 .pcie_rst
= IMX_GPIO_NR(1, 29),
464 .mezz_pwren
= IMX_GPIO_NR(2, 19),
465 .mezz_irq
= IMX_GPIO_NR(2, 18),
466 .gps_shdn
= IMX_GPIO_NR(1, 27),
467 .vidin_en
= IMX_GPIO_NR(3, 31),
468 .usb_sel
= IMX_GPIO_NR(1, 2),
469 .wdis
= IMX_GPIO_NR(7, 12),
470 .msata_en
= GP_MSATA_SEL
,
475 .gpio_pads
= gw53xx_gpio_pads
,
476 .num_pads
= ARRAY_SIZE(gw53xx_gpio_pads
)/2,
479 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
485 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
487 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
491 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
493 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
497 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
509 .pcie_rst
= IMX_GPIO_NR(1, 29),
510 .mezz_pwren
= IMX_GPIO_NR(2, 19),
511 .mezz_irq
= IMX_GPIO_NR(2, 18),
512 .gps_shdn
= IMX_GPIO_NR(1, 27),
513 .vidin_en
= IMX_GPIO_NR(3, 31),
514 .wdis
= IMX_GPIO_NR(7, 12),
515 .msata_en
= GP_MSATA_SEL
,
520 .gpio_pads
= gw54xx_gpio_pads
,
521 .num_pads
= ARRAY_SIZE(gw54xx_gpio_pads
)/2,
524 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
) },
526 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT
) },
530 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
532 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
536 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09
) },
538 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT
) },
542 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10
) },
544 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT
) },
554 .pcie_rst
= IMX_GPIO_NR(1, 29),
555 .mezz_pwren
= IMX_GPIO_NR(2, 19),
556 .mezz_irq
= IMX_GPIO_NR(2, 18),
557 .rs485en
= IMX_GPIO_NR(7, 1),
558 .vidin_en
= IMX_GPIO_NR(3, 31),
559 .dioi2c_en
= IMX_GPIO_NR(4, 5),
560 .pcie_sson
= IMX_GPIO_NR(1, 20),
561 .wdis
= IMX_GPIO_NR(5, 17),
562 .msata_en
= GP_MSATA_SEL
,
567 .gpio_pads
= gw551x_gpio_pads
,
568 .num_pads
= ARRAY_SIZE(gw551x_gpio_pads
)/2,
571 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
573 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
577 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
579 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
587 .pcie_rst
= IMX_GPIO_NR(1, 0),
588 .wdis
= IMX_GPIO_NR(7, 12),
593 .gpio_pads
= gw552x_gpio_pads
,
594 .num_pads
= ARRAY_SIZE(gw552x_gpio_pads
)/2,
597 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
603 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
605 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
609 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
611 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
615 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
627 .pcie_rst
= IMX_GPIO_NR(1, 29),
628 .usb_sel
= IMX_GPIO_NR(1, 7),
629 .wdis
= IMX_GPIO_NR(7, 12),
630 .msata_en
= GP_MSATA_SEL
,
635 .gpio_pads
= gw553x_gpio_pads
,
636 .num_pads
= ARRAY_SIZE(gw553x_gpio_pads
)/2,
639 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
645 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
647 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
651 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
653 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
657 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18
) },
659 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT
) },
668 .pcie_rst
= IMX_GPIO_NR(1, 0),
669 .vidin_en
= IMX_GPIO_NR(5, 20),
670 .wdis
= IMX_GPIO_NR(7, 12),
674 void setup_iomux_gpio(int board
, struct ventana_board_info
*info
)
678 /* iomux common to all Ventana boards */
679 SETUP_IOMUX_PADS(gw_gpio_pads
);
682 gpio_request(GP_USB_OTG_PWR
, "usbotg_pwr");
683 gpio_direction_output(GP_USB_OTG_PWR
, 0);
686 gpio_request(GP_RS232_EN
, "rs232_en");
687 gpio_direction_output(GP_RS232_EN
, 0);
689 if (board
>= GW_UNKNOWN
)
692 /* board specific iomux */
693 imx_iomux_v3_setup_multiple_pads(gpio_cfg
[board
].gpio_pads
,
694 gpio_cfg
[board
].num_pads
);
696 /* GW522x Uses GPIO3_IO23 for PCIE_RST# */
697 if (board
== GW52xx
&& info
->model
[4] == '2')
698 gpio_cfg
[board
].pcie_rst
= IMX_GPIO_NR(3, 23);
700 /* assert PCI_RST# */
701 gpio_request(gpio_cfg
[board
].pcie_rst
, "pci_rst#");
702 gpio_direction_output(gpio_cfg
[board
].pcie_rst
, 0);
704 /* turn off (active-high) user LED's */
705 for (i
= 0; i
< ARRAY_SIZE(gpio_cfg
[board
].leds
); i
++) {
707 if (gpio_cfg
[board
].leds
[i
]) {
708 sprintf(name
, "led_user%d", i
);
709 gpio_request(gpio_cfg
[board
].leds
[i
], name
);
710 gpio_direction_output(gpio_cfg
[board
].leds
[i
], 1);
714 /* MSATA Enable - default to PCI */
715 if (gpio_cfg
[board
].msata_en
) {
716 gpio_request(gpio_cfg
[board
].msata_en
, "msata_en");
717 gpio_direction_output(gpio_cfg
[board
].msata_en
, 0);
720 /* Expansion Mezzanine IO */
721 if (gpio_cfg
[board
].mezz_pwren
) {
722 gpio_request(gpio_cfg
[board
].mezz_pwren
, "mezz_pwr");
723 gpio_direction_output(gpio_cfg
[board
].mezz_pwren
, 0);
725 if (gpio_cfg
[board
].mezz_irq
) {
726 gpio_request(gpio_cfg
[board
].mezz_irq
, "mezz_irq#");
727 gpio_direction_input(gpio_cfg
[board
].mezz_irq
);
730 /* RS485 Transmit Enable */
731 if (gpio_cfg
[board
].rs485en
) {
732 gpio_request(gpio_cfg
[board
].rs485en
, "rs485_en");
733 gpio_direction_output(gpio_cfg
[board
].rs485en
, 0);
737 if (gpio_cfg
[board
].gps_shdn
) {
738 gpio_request(gpio_cfg
[board
].gps_shdn
, "gps_shdn");
739 gpio_direction_output(gpio_cfg
[board
].gps_shdn
, 1);
742 /* Analog video codec power enable */
743 if (gpio_cfg
[board
].vidin_en
) {
744 gpio_request(gpio_cfg
[board
].vidin_en
, "anavidin_en");
745 gpio_direction_output(gpio_cfg
[board
].vidin_en
, 1);
749 if (gpio_cfg
[board
].dioi2c_en
) {
750 gpio_request(gpio_cfg
[board
].dioi2c_en
, "dioi2c_dis#");
751 gpio_direction_output(gpio_cfg
[board
].dioi2c_en
, 0);
754 /* PCICK_SSON: disable spread-spectrum clock */
755 if (gpio_cfg
[board
].pcie_sson
) {
756 gpio_request(gpio_cfg
[board
].pcie_sson
, "pci_sson");
757 gpio_direction_output(gpio_cfg
[board
].pcie_sson
, 0);
760 /* USBOTG mux routing */
761 if (gpio_cfg
[board
].usb_sel
) {
762 gpio_request(gpio_cfg
[board
].usb_sel
, "usb_pcisel");
763 gpio_direction_output(gpio_cfg
[board
].usb_sel
, 0);
766 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
767 if (gpio_cfg
[board
].wdis
) {
768 gpio_request(gpio_cfg
[board
].wdis
, "wlan_dis");
769 gpio_direction_output(gpio_cfg
[board
].wdis
, 1);
772 /* sense vselect pin to see if we support uhs-i */
773 gpio_request(GP_SD3_VSELECT
, "sd3_vselect");
774 gpio_direction_input(GP_SD3_VSELECT
);
775 gpio_cfg
[board
].usd_vsel
= !gpio_get_value(GP_SD3_VSELECT
);
778 /* setup GPIO pinmux and default configuration per baseboard and env */
779 void setup_board_gpio(int board
, struct ventana_board_info
*info
)
785 int quiet
= simple_strtol(getenv("quiet"), NULL
, 10);
787 if (board
>= GW_UNKNOWN
)
791 gpio_direction_output(GP_RS232_EN
, (hwconfig("rs232")) ? 0 : 1);
794 if (gpio_cfg
[board
].msata_en
&& is_cpu_type(MXC_CPU_MX6Q
)) {
795 gpio_direction_output(GP_MSATA_SEL
,
796 (hwconfig("msata")) ? 1 : 0);
799 /* USBOTG Select (PCISKT or FrontPanel) */
800 if (gpio_cfg
[board
].usb_sel
) {
801 gpio_direction_output(gpio_cfg
[board
].usb_sel
,
802 (hwconfig("usb_pcisel")) ? 1 : 0);
806 * Configure DIO pinmux/padctl registers
807 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
809 for (i
= 0; i
< gpio_cfg
[board
].num_gpios
; i
++) {
810 struct dio_cfg
*cfg
= &gpio_cfg
[board
].dio_cfg
[i
];
811 iomux_v3_cfg_t ctrl
= DIO_PAD_CFG
;
812 unsigned cputype
= is_cpu_type(MXC_CPU_MX6Q
) ? 0 : 1;
814 if (!cfg
->gpio_padmux
[0] && !cfg
->gpio_padmux
[1])
816 sprintf(arg
, "dio%d", i
);
819 s
= hwconfig_subarg(arg
, "padctrl", &len
);
821 ctrl
= MUX_PAD_CTRL(simple_strtoul(s
, NULL
, 16)
822 & 0x1ffff) | MUX_MODE_SION
;
824 if (hwconfig_subarg_cmp(arg
, "mode", "gpio")) {
826 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i
,
827 (cfg
->gpio_param
/32)+1,
831 imx_iomux_v3_setup_pad(cfg
->gpio_padmux
[cputype
] |
833 gpio_requestf(cfg
->gpio_param
, "dio%d", i
);
834 gpio_direction_input(cfg
->gpio_param
);
835 } else if (hwconfig_subarg_cmp(arg
, "mode", "pwm") &&
837 if (!cfg
->pwm_param
) {
838 printf("DIO%d: Error: pwm config invalid\n",
843 printf("DIO%d: pwm%d\n", i
, cfg
->pwm_param
);
844 imx_iomux_v3_setup_pad(cfg
->pwm_padmux
[cputype
] |
850 if (gpio_cfg
[board
].msata_en
&& is_cpu_type(MXC_CPU_MX6Q
)) {
851 printf("MSATA: %s\n", (hwconfig("msata") ?
852 "enabled" : "disabled"));
854 printf("RS232: %s\n", (hwconfig("rs232")) ?
855 "enabled" : "disabled");
859 /* setup board specific PMIC */
860 void setup_pmic(void)
865 i2c_set_bus_num(CONFIG_I2C_PMIC
);
867 /* configure PFUZE100 PMIC */
868 if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR
)) {
869 debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR
);
870 power_pfuze100_init(CONFIG_I2C_PMIC
);
871 p
= pmic_get("PFUZE100");
872 if (p
&& !pmic_probe(p
)) {
873 pmic_reg_read(p
, PFUZE100_DEVICEID
, ®
);
874 printf("PMIC: PFUZE100 ID=0x%02x\n", reg
);
876 /* Set VGEN1 to 1.5V and enable */
877 pmic_reg_read(p
, PFUZE100_VGEN1VOL
, ®
);
878 reg
&= ~(LDO_VOL_MASK
);
879 reg
|= (LDOA_1_50V
| LDO_EN
);
880 pmic_reg_write(p
, PFUZE100_VGEN1VOL
, reg
);
882 /* Set SWBST to 5.0V and enable */
883 pmic_reg_read(p
, PFUZE100_SWBSTCON1
, ®
);
884 reg
&= ~(SWBST_MODE_MASK
| SWBST_VOL_MASK
);
885 reg
|= (SWBST_5_00V
| (SWBST_MODE_AUTO
<< SWBST_MODE_SHIFT
));
886 pmic_reg_write(p
, PFUZE100_SWBSTCON1
, reg
);
890 /* configure LTC3676 PMIC */
891 else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR
)) {
892 debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR
);
893 power_ltc3676_init(CONFIG_I2C_PMIC
);
894 p
= pmic_get("LTC3676_PMIC");
895 if (p
&& !pmic_probe(p
)) {
896 puts("PMIC: LTC3676\n");
898 * set board-specific scalar for max CPU frequency
899 * per CPU based on the LDO enabled Operating Ranges
900 * defined in the respective IMX6DQ and IMX6SDL
901 * datasheets. The voltage resulting from the R1/R2
902 * feedback inputs on Ventana is 1308mV. Note that this
903 * is a bit shy of the Vmin of 1350mV in the datasheet
904 * for LDO enabled mode but is as high as we can go.
906 * We will rely on an OS kernel driver to properly
907 * regulate these per CPU operating point and use LDO
908 * bypass mode when using the higher frequency
909 * operating points to compensate as LDO bypass mode
910 * allows the rails be 125mV lower.
912 /* mask PGOOD during SW1 transition */
913 pmic_reg_write(p
, LTC3676_DVB1B
,
914 0x1f | LTC3676_PGOOD_MASK
);
915 /* set SW1 (VDD_SOC) */
916 pmic_reg_write(p
, LTC3676_DVB1A
, 0x1f);
918 /* mask PGOOD during SW3 transition */
919 pmic_reg_write(p
, LTC3676_DVB3B
,
920 0x1f | LTC3676_PGOOD_MASK
);
921 /* set SW3 (VDD_ARM) */
922 pmic_reg_write(p
, LTC3676_DVB3A
, 0x1f);