2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/iomux-v3.h>
20 #include <asm/imx-common/mxc_i2c.h>
21 #include <asm/imx-common/boot_mode.h>
22 #include <asm/imx-common/sata.h>
23 #include <asm/imx-common/video.h>
24 #include <jffs2/load_kernel.h>
27 #include <linux/ctype.h>
28 #include <fdt_support.h>
29 #include <fsl_esdhc.h>
34 #include <power/pmic.h>
35 #include <power/ltc3676_pmic.h>
36 #include <power/pfuze100_pmic.h>
37 #include <fdt_support.h>
38 #include <jffs2/load_kernel.h>
39 #include <spi_flash.h>
42 #include "ventana_eeprom.h"
44 DECLARE_GLOBAL_DATA_PTR
;
46 /* GPIO's common to all baseboards */
47 #define GP_PHY_RST IMX_GPIO_NR(1, 30)
48 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
49 #define GP_SD3_CD IMX_GPIO_NR(7, 0)
50 #define GP_RS232_EN IMX_GPIO_NR(2, 11)
51 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
57 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
61 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
62 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
63 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
65 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
66 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
67 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
69 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
70 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
71 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
73 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
74 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
75 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
77 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
78 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
79 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
82 * EEPROM board info struct populated by read_eeprom so that we only have to
85 static struct ventana_board_info ventana_info
;
89 /* UART1: Function varies per baseboard */
90 iomux_v3_cfg_t
const uart1_pads
[] = {
91 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
92 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
95 /* UART2: Serial Console */
96 iomux_v3_cfg_t
const uart2_pads
[] = {
97 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
98 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
101 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
104 struct i2c_pads_info mx6q_i2c_pad_info0
= {
106 .i2c_mode
= MX6Q_PAD_EIM_D21__I2C1_SCL
| PC
,
107 .gpio_mode
= MX6Q_PAD_EIM_D21__GPIO3_IO21
| PC
,
108 .gp
= IMX_GPIO_NR(3, 21)
111 .i2c_mode
= MX6Q_PAD_EIM_D28__I2C1_SDA
| PC
,
112 .gpio_mode
= MX6Q_PAD_EIM_D28__GPIO3_IO28
| PC
,
113 .gp
= IMX_GPIO_NR(3, 28)
116 struct i2c_pads_info mx6dl_i2c_pad_info0
= {
118 .i2c_mode
= MX6DL_PAD_EIM_D21__I2C1_SCL
| PC
,
119 .gpio_mode
= MX6DL_PAD_EIM_D21__GPIO3_IO21
| PC
,
120 .gp
= IMX_GPIO_NR(3, 21)
123 .i2c_mode
= MX6DL_PAD_EIM_D28__I2C1_SDA
| PC
,
124 .gpio_mode
= MX6DL_PAD_EIM_D28__GPIO3_IO28
| PC
,
125 .gp
= IMX_GPIO_NR(3, 28)
129 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
130 struct i2c_pads_info mx6q_i2c_pad_info1
= {
132 .i2c_mode
= MX6Q_PAD_KEY_COL3__I2C2_SCL
| PC
,
133 .gpio_mode
= MX6Q_PAD_KEY_COL3__GPIO4_IO12
| PC
,
134 .gp
= IMX_GPIO_NR(4, 12)
137 .i2c_mode
= MX6Q_PAD_KEY_ROW3__I2C2_SDA
| PC
,
138 .gpio_mode
= MX6Q_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
139 .gp
= IMX_GPIO_NR(4, 13)
142 struct i2c_pads_info mx6dl_i2c_pad_info1
= {
144 .i2c_mode
= MX6DL_PAD_KEY_COL3__I2C2_SCL
| PC
,
145 .gpio_mode
= MX6DL_PAD_KEY_COL3__GPIO4_IO12
| PC
,
146 .gp
= IMX_GPIO_NR(4, 12)
149 .i2c_mode
= MX6DL_PAD_KEY_ROW3__I2C2_SDA
| PC
,
150 .gpio_mode
= MX6DL_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
151 .gp
= IMX_GPIO_NR(4, 13)
155 /* I2C3: Misc/Expansion */
156 struct i2c_pads_info mx6q_i2c_pad_info2
= {
158 .i2c_mode
= MX6Q_PAD_GPIO_3__I2C3_SCL
| PC
,
159 .gpio_mode
= MX6Q_PAD_GPIO_3__GPIO1_IO03
| PC
,
160 .gp
= IMX_GPIO_NR(1, 3)
163 .i2c_mode
= MX6Q_PAD_GPIO_6__I2C3_SDA
| PC
,
164 .gpio_mode
= MX6Q_PAD_GPIO_6__GPIO1_IO06
| PC
,
165 .gp
= IMX_GPIO_NR(1, 6)
168 struct i2c_pads_info mx6dl_i2c_pad_info2
= {
170 .i2c_mode
= MX6DL_PAD_GPIO_3__I2C3_SCL
| PC
,
171 .gpio_mode
= MX6DL_PAD_GPIO_3__GPIO1_IO03
| PC
,
172 .gp
= IMX_GPIO_NR(1, 3)
175 .i2c_mode
= MX6DL_PAD_GPIO_6__I2C3_SDA
| PC
,
176 .gpio_mode
= MX6DL_PAD_GPIO_6__GPIO1_IO06
| PC
,
177 .gp
= IMX_GPIO_NR(1, 6)
182 iomux_v3_cfg_t
const usdhc3_pads
[] = {
183 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
184 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
185 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
186 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
187 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
188 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
190 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
194 iomux_v3_cfg_t
const enet_pads
[] = {
195 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
196 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
197 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
198 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
199 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
200 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
201 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
202 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
|
203 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
204 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
|
205 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
206 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
207 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
208 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
209 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
210 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
211 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
|
212 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
214 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
218 iomux_v3_cfg_t
const nfc_pads
[] = {
219 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
220 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
221 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
222 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
223 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
224 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
225 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
226 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
227 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
228 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
229 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
230 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
231 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
232 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
233 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
236 #ifdef CONFIG_CMD_NAND
237 static void setup_gpmi_nand(void)
239 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
241 /* config gpmi nand iomux */
242 SETUP_IOMUX_PADS(nfc_pads
);
244 /* config gpmi and bch clock to 100 MHz */
245 clrsetbits_le32(&mxc_ccm
->cs2cdr
,
246 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK
|
247 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK
|
248 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK
,
249 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
250 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
251 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
253 /* enable gpmi and bch clock gating */
254 setbits_le32(&mxc_ccm
->CCGR4
,
255 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
256 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
257 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
258 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
259 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET
);
261 /* enable apbh clock gating */
262 setbits_le32(&mxc_ccm
->CCGR0
, MXC_CCM_CCGR0_APBHDMA_MASK
);
266 static void setup_iomux_enet(void)
268 SETUP_IOMUX_PADS(enet_pads
);
270 /* toggle PHY_RST# */
271 gpio_direction_output(GP_PHY_RST
, 0);
273 gpio_set_value(GP_PHY_RST
, 1);
276 static void setup_iomux_uart(void)
278 SETUP_IOMUX_PADS(uart1_pads
);
279 SETUP_IOMUX_PADS(uart2_pads
);
282 #ifdef CONFIG_USB_EHCI_MX6
283 iomux_v3_cfg_t
const usb_pads
[] = {
284 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID
| MUX_PAD_CTRL(DIO_PAD_CTRL
)),
285 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC
| MUX_PAD_CTRL(DIO_PAD_CTRL
)),
287 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22
| MUX_PAD_CTRL(DIO_PAD_CTRL
)),
290 int board_ehci_hcd_init(int port
)
292 struct ventana_board_info
*info
= &ventana_info
;
294 SETUP_IOMUX_PADS(usb_pads
);
296 /* Reset USB HUB (present on GW54xx/GW53xx) */
297 switch (info
->model
[3]) {
298 case '3': /* GW53xx */
299 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09
|
300 MUX_PAD_CTRL(NO_PAD_CTRL
));
301 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
303 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
305 case '4': /* GW54xx */
306 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16
|
307 MUX_PAD_CTRL(NO_PAD_CTRL
));
308 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
310 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
317 int board_ehci_power(int port
, int on
)
321 gpio_set_value(GP_USB_OTG_PWR
, on
);
324 #endif /* CONFIG_USB_EHCI_MX6 */
326 #ifdef CONFIG_FSL_ESDHC
327 struct fsl_esdhc_cfg usdhc_cfg
= { USDHC3_BASE_ADDR
};
329 int board_mmc_getcd(struct mmc
*mmc
)
332 gpio_direction_input(GP_SD3_CD
);
333 return !gpio_get_value(GP_SD3_CD
);
336 int board_mmc_init(bd_t
*bis
)
338 /* Only one USDHC controller on Ventana */
339 SETUP_IOMUX_PADS(usdhc3_pads
);
340 usdhc_cfg
.sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
341 usdhc_cfg
.max_bus_width
= 4;
343 return fsl_esdhc_initialize(bis
, &usdhc_cfg
);
345 #endif /* CONFIG_FSL_ESDHC */
347 #ifdef CONFIG_MXC_SPI
348 iomux_v3_cfg_t
const ecspi1_pads
[] = {
350 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
351 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
352 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
353 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
356 static void setup_spi(void)
358 gpio_direction_output(CONFIG_SF_DEFAULT_CS
, 1);
359 SETUP_IOMUX_PADS(ecspi1_pads
);
363 /* configure eth0 PHY board-specific LED behavior */
364 int board_phy_config(struct phy_device
*phydev
)
369 if (phydev
->phy_id
== 0x1410dd1) {
371 * Page 3, Register 16: LED[2:0] Function Control Register
372 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
373 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
375 phy_write(phydev
, MDIO_DEVAD_NONE
, 22, 3);
376 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 16);
379 phy_write(phydev
, MDIO_DEVAD_NONE
, 16, val
);
380 phy_write(phydev
, MDIO_DEVAD_NONE
, 22, 0);
383 if (phydev
->drv
->config
)
384 phydev
->drv
->config(phydev
);
389 int board_eth_init(bd_t
*bis
)
393 #ifdef CONFIG_FEC_MXC
398 /* For otg ethernet*/
399 usb_eth_initialize(bis
);
405 #if defined(CONFIG_VIDEO_IPUV3)
407 static void enable_hdmi(struct display_info_t
const *dev
)
409 imx_enable_hdmi_phy();
412 static int detect_i2c(struct display_info_t
const *dev
)
414 return i2c_set_bus_num(dev
->bus
) == 0 &&
415 i2c_probe(dev
->addr
) == 0;
418 static void enable_lvds(struct display_info_t
const *dev
)
420 struct iomuxc
*iomux
= (struct iomuxc
*)
423 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
424 u32 reg
= readl(&iomux
->gpr
[2]);
425 reg
|= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
;
426 writel(reg
, &iomux
->gpr
[2]);
428 /* Enable Backlight */
429 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18
| MUX_PAD_CTRL(NO_PAD_CTRL
));
430 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
433 struct display_info_t
const displays
[] = {{
437 .pixfmt
= IPU_PIX_FMT_RGB24
,
438 .detect
= detect_hdmi
,
439 .enable
= enable_hdmi
,
453 .vmode
= FB_VMODE_NONINTERLACED
455 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
458 .pixfmt
= IPU_PIX_FMT_LVDS666
,
459 .detect
= detect_i2c
,
460 .enable
= enable_lvds
,
462 .name
= "Hannstar-XGA",
474 .vmode
= FB_VMODE_NONINTERLACED
476 size_t display_count
= ARRAY_SIZE(displays
);
478 static void setup_display(void)
480 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
481 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
486 /* Turn on LDB0,IPU,IPU DI0 clocks */
487 reg
= __raw_readl(&mxc_ccm
->CCGR3
);
488 reg
|= MXC_CCM_CCGR3_LDB_DI0_MASK
;
489 writel(reg
, &mxc_ccm
->CCGR3
);
491 /* set LDB0, LDB1 clk select to 011/011 */
492 reg
= readl(&mxc_ccm
->cs2cdr
);
493 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
494 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
);
495 reg
|= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
)
496 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
);
497 writel(reg
, &mxc_ccm
->cs2cdr
);
499 reg
= readl(&mxc_ccm
->cscmr2
);
500 reg
|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV
;
501 writel(reg
, &mxc_ccm
->cscmr2
);
503 reg
= readl(&mxc_ccm
->chsccdr
);
504 reg
|= (CHSCCDR_CLK_SEL_LDB_DI0
505 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
);
506 writel(reg
, &mxc_ccm
->chsccdr
);
508 reg
= IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
509 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
510 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
511 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
512 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
513 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
514 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
515 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
516 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
;
517 writel(reg
, &iomux
->gpr
[2]);
519 reg
= readl(&iomux
->gpr
[3]);
520 reg
= (reg
& ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
)
521 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
522 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET
);
523 writel(reg
, &iomux
->gpr
[3]);
525 /* Backlight CABEN on LVDS connector */
526 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10
| MUX_PAD_CTRL(NO_PAD_CTRL
));
527 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
529 #endif /* CONFIG_VIDEO_IPUV3 */
532 * Baseboard specific GPIO
535 /* common to add baseboards */
536 static iomux_v3_cfg_t
const gw_gpio_pads
[] = {
538 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
540 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
544 static iomux_v3_cfg_t
const gwproto_gpio_pads
[] = {
546 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
548 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
550 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
552 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
554 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
556 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
558 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
560 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
562 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
564 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
567 static iomux_v3_cfg_t
const gw51xx_gpio_pads
[] = {
569 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
571 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
573 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
575 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
578 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
580 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
582 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
585 static iomux_v3_cfg_t
const gw52xx_gpio_pads
[] = {
587 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
589 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
591 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
593 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
596 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
598 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
600 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
602 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
604 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
607 static iomux_v3_cfg_t
const gw53xx_gpio_pads
[] = {
609 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
611 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
613 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
615 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
618 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
620 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
622 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
624 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
627 static iomux_v3_cfg_t
const gw54xx_gpio_pads
[] = {
629 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
631 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
633 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
635 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
637 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
639 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
641 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
643 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
645 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
647 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
649 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
653 * each baseboard has 4 user configurable Digital IO lines which can
654 * be pinmuxed as a GPIO or in some cases a PWM
657 iomux_v3_cfg_t gpio_padmux
[2];
659 iomux_v3_cfg_t pwm_padmux
[2];
665 iomux_v3_cfg_t
const *gpio_pads
;
668 struct dio_cfg dio_cfg
[4];
669 /* various gpios (0 if non-existent) */
682 struct ventana gpio_cfg
[] = {
685 .gpio_pads
= gw54xx_gpio_pads
,
686 .num_pads
= ARRAY_SIZE(gw54xx_gpio_pads
)/2,
689 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
) },
691 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT
) },
695 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
697 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
701 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09
) },
703 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT
) },
707 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10
) },
709 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT
) },
718 .pcie_rst
= IMX_GPIO_NR(1, 29),
719 .mezz_pwren
= IMX_GPIO_NR(4, 7),
720 .mezz_irq
= IMX_GPIO_NR(4, 9),
721 .rs485en
= IMX_GPIO_NR(3, 24),
722 .dioi2c_en
= IMX_GPIO_NR(4, 5),
723 .pcie_sson
= IMX_GPIO_NR(1, 20),
728 .gpio_pads
= gw51xx_gpio_pads
,
729 .num_pads
= ARRAY_SIZE(gw51xx_gpio_pads
)/2,
732 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
738 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
740 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
744 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
746 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
750 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18
) },
752 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT
) },
760 .pcie_rst
= IMX_GPIO_NR(1, 0),
761 .mezz_pwren
= IMX_GPIO_NR(2, 19),
762 .mezz_irq
= IMX_GPIO_NR(2, 18),
763 .gps_shdn
= IMX_GPIO_NR(1, 2),
764 .vidin_en
= IMX_GPIO_NR(5, 20),
769 .gpio_pads
= gw52xx_gpio_pads
,
770 .num_pads
= ARRAY_SIZE(gw52xx_gpio_pads
)/2,
773 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
779 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
781 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
785 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
787 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
791 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
802 .pcie_rst
= IMX_GPIO_NR(1, 29),
803 .mezz_pwren
= IMX_GPIO_NR(2, 19),
804 .mezz_irq
= IMX_GPIO_NR(2, 18),
805 .gps_shdn
= IMX_GPIO_NR(1, 27),
806 .vidin_en
= IMX_GPIO_NR(3, 31),
807 .usb_sel
= IMX_GPIO_NR(1, 2),
812 .gpio_pads
= gw53xx_gpio_pads
,
813 .num_pads
= ARRAY_SIZE(gw53xx_gpio_pads
)/2,
816 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16
) },
822 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
824 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
828 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17
) },
830 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT
) },
834 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20
) },
845 .pcie_rst
= IMX_GPIO_NR(1, 29),
846 .mezz_pwren
= IMX_GPIO_NR(2, 19),
847 .mezz_irq
= IMX_GPIO_NR(2, 18),
848 .gps_shdn
= IMX_GPIO_NR(1, 27),
849 .vidin_en
= IMX_GPIO_NR(3, 31),
854 .gpio_pads
= gw54xx_gpio_pads
,
855 .num_pads
= ARRAY_SIZE(gw54xx_gpio_pads
)/2,
858 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09
) },
860 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT
) },
864 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19
) },
866 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT
) },
870 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09
) },
872 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT
) },
876 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10
) },
878 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT
) },
887 .pcie_rst
= IMX_GPIO_NR(1, 29),
888 .mezz_pwren
= IMX_GPIO_NR(2, 19),
889 .mezz_irq
= IMX_GPIO_NR(2, 18),
890 .rs485en
= IMX_GPIO_NR(7, 1),
891 .vidin_en
= IMX_GPIO_NR(3, 31),
892 .dioi2c_en
= IMX_GPIO_NR(4, 5),
893 .pcie_sson
= IMX_GPIO_NR(1, 20),
897 /* setup board specific PMIC */
898 int power_init_board(void)
903 /* configure PFUZE100 PMIC */
904 if (board_type
== GW54xx
|| board_type
== GW54proto
) {
905 power_pfuze100_init(I2C_PMIC
);
906 p
= pmic_get("PFUZE100_PMIC");
907 if (p
&& !pmic_probe(p
)) {
908 pmic_reg_read(p
, PFUZE100_DEVICEID
, ®
);
909 printf("PMIC: PFUZE100 ID=0x%02x\n", reg
);
911 /* Set VGEN1 to 1.5V and enable */
912 pmic_reg_read(p
, PFUZE100_VGEN1VOL
, ®
);
913 reg
&= ~(LDO_VOL_MASK
);
914 reg
|= (LDOA_1_50V
| LDO_EN
);
915 pmic_reg_write(p
, PFUZE100_VGEN1VOL
, reg
);
917 /* Set SWBST to 5.0V and enable */
918 pmic_reg_read(p
, PFUZE100_SWBSTCON1
, ®
);
919 reg
&= ~(SWBST_MODE_MASK
| SWBST_VOL_MASK
);
920 reg
|= (SWBST_5_00V
| SWBST_MODE_AUTO
);
921 pmic_reg_write(p
, PFUZE100_SWBSTCON1
, reg
);
925 /* configure LTC3676 PMIC */
927 power_ltc3676_init(I2C_PMIC
);
928 p
= pmic_get("LTC3676_PMIC");
929 if (p
&& !pmic_probe(p
)) {
930 puts("PMIC: LTC3676\n");
931 /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
932 if (is_cpu_type(MXC_CPU_MX6Q
)) {
933 /* mask PGOOD during SW1 transition */
934 reg
= 0x1d | LTC3676_PGOOD_MASK
;
935 pmic_reg_write(p
, LTC3676_DVB1B
, reg
);
936 /* set SW1 (VDD_SOC) to 1259mV */
938 pmic_reg_write(p
, LTC3676_DVB1A
, reg
);
940 /* mask PGOOD during SW3 transition */
941 reg
= 0x1d | LTC3676_PGOOD_MASK
;
942 pmic_reg_write(p
, LTC3676_DVB3B
, reg
);
943 /*set SW3 (VDD_ARM) to 1259mV */
945 pmic_reg_write(p
, LTC3676_DVB3A
, reg
);
953 /* setup GPIO pinmux and default configuration per baseboard */
954 static void setup_board_gpio(int board
)
956 struct ventana_board_info
*info
= &ventana_info
;
961 int quiet
= simple_strtol(getenv("quiet"), NULL
, 10);
963 if (board
>= GW_UNKNOWN
)
967 gpio_direction_output(GP_RS232_EN
, (hwconfig("rs232")) ? 0 : 1);
970 if (is_cpu_type(MXC_CPU_MX6Q
) &&
971 test_bit(EECONFIG_SATA
, info
->config
)) {
972 gpio_direction_output(GP_MSATA_SEL
,
973 (hwconfig("msata")) ? 1 : 0);
975 gpio_direction_output(GP_MSATA_SEL
, 0);
979 * assert PCI_RST# (released by OS when clock is valid)
980 * TODO: figure out why leaving this de-asserted from PCI scan on boot
981 * causes linux pcie driver to hang during enumeration
983 gpio_direction_output(gpio_cfg
[board
].pcie_rst
, 0);
985 /* turn off (active-high) user LED's */
986 for (i
= 0; i
< 4; i
++) {
987 if (gpio_cfg
[board
].leds
[i
])
988 gpio_direction_output(gpio_cfg
[board
].leds
[i
], 1);
991 /* Expansion Mezzanine IO */
992 gpio_direction_output(gpio_cfg
[board
].mezz_pwren
, 0);
993 gpio_direction_input(gpio_cfg
[board
].mezz_irq
);
995 /* RS485 Transmit Enable */
996 if (gpio_cfg
[board
].rs485en
)
997 gpio_direction_output(gpio_cfg
[board
].rs485en
, 0);
1000 if (gpio_cfg
[board
].gps_shdn
)
1001 gpio_direction_output(gpio_cfg
[board
].gps_shdn
, 1);
1003 /* Analog video codec power enable */
1004 if (gpio_cfg
[board
].vidin_en
)
1005 gpio_direction_output(gpio_cfg
[board
].vidin_en
, 1);
1008 if (gpio_cfg
[board
].dioi2c_en
)
1009 gpio_direction_output(gpio_cfg
[board
].dioi2c_en
, 0);
1011 /* PCICK_SSON: disable spread-spectrum clock */
1012 if (gpio_cfg
[board
].pcie_sson
)
1013 gpio_direction_output(gpio_cfg
[board
].pcie_sson
, 0);
1015 /* USBOTG Select (PCISKT or FrontPanel) */
1016 if (gpio_cfg
[board
].usb_sel
)
1017 gpio_direction_output(gpio_cfg
[board
].usb_sel
, 0);
1020 * Configure DIO pinmux/padctl registers
1021 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1023 for (i
= 0; i
< 4; i
++) {
1024 struct dio_cfg
*cfg
= &gpio_cfg
[board
].dio_cfg
[i
];
1025 unsigned ctrl
= DIO_PAD_CTRL
;
1026 unsigned cputype
= is_cpu_type(MXC_CPU_MX6Q
) ? 0 : 1;
1028 sprintf(arg
, "dio%d", i
);
1031 s
= hwconfig_subarg(arg
, "padctrl", &len
);
1033 ctrl
= simple_strtoul(s
, NULL
, 16) & 0x3ffff;
1034 if (hwconfig_subarg_cmp(arg
, "mode", "gpio")) {
1036 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i
,
1037 (cfg
->gpio_param
/32)+1,
1041 imx_iomux_v3_setup_pad(cfg
->gpio_padmux
[cputype
] |
1042 MUX_PAD_CTRL(ctrl
));
1043 gpio_direction_input(cfg
->gpio_param
);
1044 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1047 printf("DIO%d: pwm%d\n", i
, cfg
->pwm_param
);
1048 imx_iomux_v3_setup_pad(cfg
->pwm_padmux
[cputype
] |
1049 MUX_PAD_CTRL(ctrl
));
1054 if (is_cpu_type(MXC_CPU_MX6Q
) &&
1055 (test_bit(EECONFIG_SATA
, info
->config
))) {
1056 printf("MSATA: %s\n", (hwconfig("msata") ?
1057 "enabled" : "disabled"));
1059 printf("RS232: %s\n", (hwconfig("rs232")) ?
1060 "enabled" : "disabled");
1064 #if defined(CONFIG_CMD_PCI)
1065 int imx6_pcie_toggle_reset(void)
1067 if (board_type
< GW_UNKNOWN
) {
1068 uint pin
= gpio_cfg
[board_type
].pcie_rst
;
1069 gpio_direction_output(pin
, 0);
1071 gpio_direction_output(pin
, 1);
1075 #endif /* CONFIG_CMD_PCI */
1077 #ifdef CONFIG_SERIAL_TAG
1079 * called when setting up ATAGS before booting kernel
1080 * populate serialnum from the following (in order of priority):
1084 void get_board_serial(struct tag_serialnr
*serialnr
)
1086 char *serial
= getenv("serial#");
1090 serialnr
->low
= simple_strtoul(serial
, NULL
, 10);
1091 } else if (ventana_info
.model
[0]) {
1093 serialnr
->low
= ventana_info
.serial
;
1105 /* called from SPL board_init_f() */
1106 int board_early_init_f(void)
1109 gpio_direction_output(GP_USB_OTG_PWR
, 0); /* OTG power off */
1111 #if defined(CONFIG_VIDEO_IPUV3)
1119 gd
->ram_size
= imx_ddr_size();
1123 int board_init(void)
1125 struct iomuxc_base_regs
*const iomuxc_regs
1126 = (struct iomuxc_base_regs
*)IOMUXC_BASE_ADDR
;
1128 clrsetbits_le32(&iomuxc_regs
->gpr
[1],
1129 IOMUXC_GPR1_OTG_ID_MASK
,
1130 IOMUXC_GPR1_OTG_ID_GPIO1
);
1132 /* address of linux boot parameters */
1133 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
1135 #ifdef CONFIG_CMD_NAND
1138 #ifdef CONFIG_MXC_SPI
1141 if (is_cpu_type(MXC_CPU_MX6Q
)) {
1142 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info0
);
1143 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info1
);
1144 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6q_i2c_pad_info2
);
1146 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info0
);
1147 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info1
);
1148 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &mx6dl_i2c_pad_info2
);
1151 #ifdef CONFIG_CMD_SATA
1154 /* read Gateworks EEPROM into global struct (used later) */
1155 board_type
= read_eeprom(I2C_GSC
, &ventana_info
);
1157 /* board-specifc GPIO iomux */
1158 SETUP_IOMUX_PADS(gw_gpio_pads
);
1159 if (board_type
< GW_UNKNOWN
) {
1160 iomux_v3_cfg_t
const *p
= gpio_cfg
[board_type
].gpio_pads
;
1161 int count
= gpio_cfg
[board_type
].num_pads
;
1163 imx_iomux_v3_setup_multiple_pads(p
, count
);
1169 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1171 * called during late init (after relocation and after board_init())
1172 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1175 int checkboard(void)
1177 struct ventana_board_info
*info
= &ventana_info
;
1178 unsigned char buf
[4];
1180 int quiet
; /* Quiet or minimal output mode */
1183 p
= getenv("quiet");
1185 quiet
= simple_strtol(p
, NULL
, 10);
1187 setenv("quiet", "0");
1189 puts("\nGateworks Corporation Copyright 2014\n");
1190 if (info
->model
[0]) {
1191 printf("Model: %s\n", info
->model
);
1192 printf("MFGDate: %02x-%02x-%02x%02x\n",
1193 info
->mfgdate
[0], info
->mfgdate
[1],
1194 info
->mfgdate
[2], info
->mfgdate
[3]);
1195 printf("Serial:%d\n", info
->serial
);
1197 puts("Invalid EEPROM - board will not function fully\n");
1202 /* Display GSC firmware revision/CRC/status */
1203 i2c_set_bus_num(I2C_GSC
);
1204 if (!gsc_i2c_read(GSC_SC_ADDR
, GSC_SC_FWVER
, 1, buf
, 1)) {
1205 printf("GSC: v%d", buf
[0]);
1206 if (!gsc_i2c_read(GSC_SC_ADDR
, GSC_SC_STATUS
, 1, buf
, 4)) {
1207 printf(" 0x%04x", buf
[2] | buf
[3]<<8); /* CRC */
1208 printf(" 0x%02x", buf
[0]); /* irq status */
1213 if (!gsc_i2c_read(GSC_RTC_ADDR
, 0x00, 1, buf
, 4)) {
1215 buf
[0] | buf
[1]<<8 | buf
[2]<<16 | buf
[3]<<24);
1222 #ifdef CONFIG_CMD_BMODE
1224 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1225 * see Table 8-11 and Table 5-9
1226 * BOOT_CFG1[7] = 1 (boot from NAND)
1227 * BOOT_CFG1[5] = 0 - raw NAND
1228 * BOOT_CFG1[4] = 0 - default pad settings
1229 * BOOT_CFG1[3:2] = 00 - devices = 1
1230 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1231 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1232 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1233 * BOOT_CFG2[0] = 0 - Reset time 12ms
1235 static const struct boot_mode board_boot_modes
[] = {
1236 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1237 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1243 int misc_init_r(void)
1245 struct ventana_board_info
*info
= &ventana_info
;
1248 /* set env vars based on EEPROM data */
1249 if (ventana_info
.model
[0]) {
1250 char str
[16], fdt
[36];
1252 const char *cputype
= "";
1256 * FDT name will be prefixed with CPU type. Three versions
1257 * will be created each increasingly generic and bootloader
1258 * env scripts will try loading each from most specific to
1261 if (is_cpu_type(MXC_CPU_MX6Q
) ||
1262 is_cpu_type(MXC_CPU_MX6D
))
1264 else if (is_cpu_type(MXC_CPU_MX6DL
) ||
1265 is_cpu_type(MXC_CPU_MX6SOLO
))
1267 memset(str
, 0, sizeof(str
));
1268 for (i
= 0; i
< (sizeof(str
)-1) && info
->model
[i
]; i
++)
1269 str
[i
] = tolower(info
->model
[i
]);
1270 if (!getenv("model"))
1271 setenv("model", str
);
1272 if (!getenv("fdt_file")) {
1273 sprintf(fdt
, "%s-%s.dtb", cputype
, str
);
1274 setenv("fdt_file", fdt
);
1276 p
= strchr(str
, '-');
1280 setenv("model_base", str
);
1281 if (!getenv("fdt_file1")) {
1282 sprintf(fdt
, "%s-%s.dtb", cputype
, str
);
1283 setenv("fdt_file1", fdt
);
1288 if (!getenv("fdt_file2")) {
1289 sprintf(fdt
, "%s-%s.dtb", cputype
, str
);
1290 setenv("fdt_file2", fdt
);
1294 /* initialize env from EEPROM */
1295 if (test_bit(EECONFIG_ETH0
, info
->config
) &&
1296 !getenv("ethaddr")) {
1297 eth_setenv_enetaddr("ethaddr", info
->mac0
);
1299 if (test_bit(EECONFIG_ETH1
, info
->config
) &&
1300 !getenv("eth1addr")) {
1301 eth_setenv_enetaddr("eth1addr", info
->mac1
);
1304 /* board serial-number */
1305 sprintf(str
, "%6d", info
->serial
);
1306 setenv("serial#", str
);
1310 /* setup baseboard specific GPIO pinmux and config */
1311 setup_board_gpio(board_type
);
1313 #ifdef CONFIG_CMD_BMODE
1314 add_board_boot_modes(board_boot_modes
);
1318 * The Gateworks System Controller implements a boot
1319 * watchdog (always enabled) as a workaround for IMX6 boot related
1321 * ERR005768 - no fix
1322 * ERR006282 - fixed in silicon r1.3
1323 * ERR007117 - fixed in silicon r1.3
1324 * ERR007220 - fixed in silicon r1.3
1325 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1327 * Disable the boot watchdog and display/clear the timeout flag if set
1329 i2c_set_bus_num(I2C_GSC
);
1330 if (!gsc_i2c_read(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1)) {
1331 reg
|= (1 << GSC_SC_CTRL1_WDDIS
);
1332 if (gsc_i2c_write(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
1333 puts("Error: could not disable GSC Watchdog\n");
1335 puts("Error: could not disable GSC Watchdog\n");
1337 if (!gsc_i2c_read(GSC_SC_ADDR
, GSC_SC_STATUS
, 1, ®
, 1)) {
1338 if (reg
& (1 << GSC_SC_IRQ_WATCHDOG
)) { /* watchdog timeout */
1339 puts("GSC boot watchdog timeout detected");
1340 reg
&= ~(1 << GSC_SC_IRQ_WATCHDOG
); /* clear flag */
1341 gsc_i2c_write(GSC_SC_ADDR
, GSC_SC_STATUS
, 1, ®
, 1);
1348 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1350 /* FDT aliases associated with EEPROM config bits */
1351 const char *fdt_aliases
[] = {
1419 * called prior to booting kernel or by 'fdt boardsetup' command
1421 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1422 * - mtd partitions based on mtdparts/mtdids env
1423 * - system-serial (board serial num from EEPROM)
1424 * - board (full model from EEPROM)
1425 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1427 void ft_board_setup(void *blob
, bd_t
*bd
)
1430 struct ventana_board_info
*info
= &ventana_info
;
1431 struct node_info nodes
[] = {
1432 { "sst,w25q256", MTD_DEV_TYPE_NOR
, }, /* SPI flash */
1433 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND
, }, /* NAND flash */
1435 const char *model
= getenv("model");
1437 if (getenv("fdt_noauto")) {
1438 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1442 /* Update partition nodes using info from mtdparts env var */
1443 puts(" Updating MTD partitions...\n");
1444 fdt_fixup_mtdparts(blob
, nodes
, ARRAY_SIZE(nodes
));
1447 puts("invalid board info: Leaving FDT fully enabled\n");
1450 printf(" Adjusting FDT per EEPROM for %s...\n", model
);
1452 /* board serial number */
1453 fdt_setprop(blob
, 0, "system-serial", getenv("serial#"),
1454 strlen(getenv("serial#")) + 1);
1456 /* board (model contains model from device-tree) */
1457 fdt_setprop(blob
, 0, "board", info
->model
,
1458 strlen((const char *)info
->model
) + 1);
1461 * Peripheral Config:
1462 * remove nodes by alias path if EEPROM config tells us the
1463 * peripheral is not loaded on the board.
1465 for (bit
= 0; bit
< 64; bit
++) {
1466 if (!test_bit(bit
, info
->config
))
1467 fdt_del_node_and_alias(blob
, fdt_aliases
[bit
]);
1470 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */