2 * Copyright 2015 Timesys Corporation
3 * Copyright 2015 General Electric Company
4 * Copyright 2012 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <linux/errno.h>
15 #include <asm/mach-imx/mxc_i2c.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/video.h>
20 #include <fsl_esdhc.h>
23 #include <asm/arch/mxc_hdmi.h>
24 #include <asm/arch/crm_regs.h>
26 #include <asm/arch/sys_proto.h>
31 #include "vpd_reader.h"
32 DECLARE_GLOBAL_DATA_PTR
;
34 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
35 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
36 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
39 #ifndef CONFIG_SYS_I2C_EEPROM_BUS
40 #define CONFIG_SYS_I2C_EEPROM_BUS 2
43 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
47 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
49 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
52 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
53 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
55 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
58 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
61 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
62 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
64 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
65 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
67 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
69 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
71 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
75 gd
->ram_size
= imx_ddr_size();
80 static iomux_v3_cfg_t
const uart3_pads
[] = {
81 MX6_PAD_EIM_D31__UART3_RTS_B
| MUX_PAD_CTRL(UART_PAD_CTRL
),
82 MX6_PAD_EIM_D23__UART3_CTS_B
| MUX_PAD_CTRL(UART_PAD_CTRL
),
83 MX6_PAD_EIM_D24__UART3_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
84 MX6_PAD_EIM_D25__UART3_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
87 static iomux_v3_cfg_t
const uart4_pads
[] = {
88 MX6_PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
89 MX6_PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
92 static iomux_v3_cfg_t
const enet_pads
[] = {
93 MX6_PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
94 MX6_PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
95 MX6_PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
96 MX6_PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
97 MX6_PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
98 MX6_PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
99 MX6_PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
100 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
101 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL
),
102 MX6_PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
103 MX6_PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
104 MX6_PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
105 MX6_PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
106 MX6_PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
107 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
108 /* AR8033 PHY Reset */
109 MX6_PAD_ENET_TX_EN__GPIO1_IO28
| MUX_PAD_CTRL(NO_PAD_CTRL
),
112 static void setup_iomux_enet(void)
114 imx_iomux_v3_setup_multiple_pads(enet_pads
, ARRAY_SIZE(enet_pads
));
116 /* Reset AR8033 PHY */
117 gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
119 gpio_set_value(IMX_GPIO_NR(1, 28), 1);
123 static iomux_v3_cfg_t
const usdhc2_pads
[] = {
124 MX6_PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
125 MX6_PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
126 MX6_PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
127 MX6_PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
128 MX6_PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
129 MX6_PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
130 MX6_PAD_GPIO_4__GPIO1_IO04
| MUX_PAD_CTRL(NO_PAD_CTRL
),
133 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
134 MX6_PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
135 MX6_PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
136 MX6_PAD_SD3_RST__SD3_RESET
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
137 MX6_PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
138 MX6_PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
139 MX6_PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
140 MX6_PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
141 MX6_PAD_SD3_DAT4__SD3_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
142 MX6_PAD_SD3_DAT5__SD3_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
143 MX6_PAD_SD3_DAT6__SD3_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
144 MX6_PAD_SD3_DAT7__SD3_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
147 static iomux_v3_cfg_t
const usdhc4_pads
[] = {
148 MX6_PAD_SD4_CLK__SD4_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
149 MX6_PAD_SD4_CMD__SD4_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
150 MX6_PAD_SD4_DAT0__SD4_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
151 MX6_PAD_SD4_DAT1__SD4_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
152 MX6_PAD_SD4_DAT2__SD4_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
153 MX6_PAD_SD4_DAT3__SD4_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
154 MX6_PAD_SD4_DAT4__SD4_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
155 MX6_PAD_SD4_DAT5__SD4_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
156 MX6_PAD_SD4_DAT6__SD4_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
157 MX6_PAD_SD4_DAT7__SD4_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
158 MX6_PAD_NANDF_CS0__GPIO6_IO11
| MUX_PAD_CTRL(NO_PAD_CTRL
),
159 MX6_PAD_NANDF_CS1__GPIO6_IO14
| MUX_PAD_CTRL(NO_PAD_CTRL
),
162 static iomux_v3_cfg_t
const ecspi1_pads
[] = {
163 MX6_PAD_EIM_D16__ECSPI1_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
164 MX6_PAD_EIM_D17__ECSPI1_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
165 MX6_PAD_EIM_D18__ECSPI1_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
),
166 MX6_PAD_EIM_EB2__GPIO2_IO30
| MUX_PAD_CTRL(NO_PAD_CTRL
),
169 static struct i2c_pads_info i2c_pad_info1
= {
171 .i2c_mode
= MX6_PAD_CSI0_DAT9__I2C1_SCL
| I2C_PAD
,
172 .gpio_mode
= MX6_PAD_CSI0_DAT9__GPIO5_IO27
| I2C_PAD
,
173 .gp
= IMX_GPIO_NR(5, 27)
176 .i2c_mode
= MX6_PAD_CSI0_DAT8__I2C1_SDA
| I2C_PAD
,
177 .gpio_mode
= MX6_PAD_CSI0_DAT8__GPIO5_IO26
| I2C_PAD
,
178 .gp
= IMX_GPIO_NR(5, 26)
182 static struct i2c_pads_info i2c_pad_info2
= {
184 .i2c_mode
= MX6_PAD_KEY_COL3__I2C2_SCL
| I2C_PAD
,
185 .gpio_mode
= MX6_PAD_KEY_COL3__GPIO4_IO12
| I2C_PAD
,
186 .gp
= IMX_GPIO_NR(4, 12)
189 .i2c_mode
= MX6_PAD_KEY_ROW3__I2C2_SDA
| I2C_PAD
,
190 .gpio_mode
= MX6_PAD_KEY_ROW3__GPIO4_IO13
| I2C_PAD
,
191 .gp
= IMX_GPIO_NR(4, 13)
195 static struct i2c_pads_info i2c_pad_info3
= {
197 .i2c_mode
= MX6_PAD_GPIO_3__I2C3_SCL
| I2C_PAD
,
198 .gpio_mode
= MX6_PAD_GPIO_3__GPIO1_IO03
| I2C_PAD
,
199 .gp
= IMX_GPIO_NR(1, 3)
202 .i2c_mode
= MX6_PAD_GPIO_6__I2C3_SDA
| I2C_PAD
,
203 .gpio_mode
= MX6_PAD_GPIO_6__GPIO1_IO06
| I2C_PAD
,
204 .gp
= IMX_GPIO_NR(1, 6)
208 #ifdef CONFIG_MXC_SPI
209 int board_spi_cs_gpio(unsigned bus
, unsigned cs
)
211 return (bus
== 0 && cs
== 0) ? (IMX_GPIO_NR(2, 30)) : -1;
214 static void setup_spi(void)
216 imx_iomux_v3_setup_multiple_pads(ecspi1_pads
, ARRAY_SIZE(ecspi1_pads
));
220 static iomux_v3_cfg_t
const pcie_pads
[] = {
221 MX6_PAD_GPIO_5__GPIO1_IO05
| MUX_PAD_CTRL(NO_PAD_CTRL
),
222 MX6_PAD_GPIO_17__GPIO7_IO12
| MUX_PAD_CTRL(NO_PAD_CTRL
),
225 static void setup_pcie(void)
227 imx_iomux_v3_setup_multiple_pads(pcie_pads
, ARRAY_SIZE(pcie_pads
));
230 static void setup_iomux_uart(void)
232 imx_iomux_v3_setup_multiple_pads(uart3_pads
, ARRAY_SIZE(uart3_pads
));
233 imx_iomux_v3_setup_multiple_pads(uart4_pads
, ARRAY_SIZE(uart4_pads
));
236 #ifdef CONFIG_FSL_ESDHC
237 struct fsl_esdhc_cfg usdhc_cfg
[3] = {
243 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
244 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
246 int board_mmc_getcd(struct mmc
*mmc
)
248 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
251 switch (cfg
->esdhc_base
) {
252 case USDHC2_BASE_ADDR
:
253 ret
= !gpio_get_value(USDHC2_CD_GPIO
);
255 case USDHC3_BASE_ADDR
:
256 ret
= 1; /* eMMC is always present */
258 case USDHC4_BASE_ADDR
:
259 ret
= !gpio_get_value(USDHC4_CD_GPIO
);
266 int board_mmc_init(bd_t
*bis
)
271 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
274 imx_iomux_v3_setup_multiple_pads(
275 usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
276 gpio_direction_input(USDHC2_CD_GPIO
);
277 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
280 imx_iomux_v3_setup_multiple_pads(
281 usdhc3_pads
, ARRAY_SIZE(usdhc3_pads
));
282 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
285 imx_iomux_v3_setup_multiple_pads(
286 usdhc4_pads
, ARRAY_SIZE(usdhc4_pads
));
287 gpio_direction_input(USDHC4_CD_GPIO
);
288 usdhc_cfg
[2].sdhc_clk
= mxc_get_clock(MXC_ESDHC4_CLK
);
291 printf("Warning: you configured more USDHC controllers\n"
292 "(%d) then supported by the board (%d)\n",
293 i
+ 1, CONFIG_SYS_FSL_USDHC_NUM
);
297 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
306 static int mx6_rgmii_rework(struct phy_device
*phydev
)
308 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
309 /* set device address 0x7 */
310 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x7);
311 /* offset 0x8016: CLK_25M Clock Select */
312 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, 0x8016);
313 /* enable register write, no post increment, address 0x7 */
314 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x4007);
315 /* set to 125 MHz from local PLL source */
316 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, 0x18);
318 /* rgmii tx clock delay enable */
319 /* set debug port address: SerDes Test and System Mode Control */
320 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x05);
321 /* enable rgmii tx clock delay */
322 /* set the reserved bits to avoid board specific voltage peak issue*/
323 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x3D47);
328 int board_phy_config(struct phy_device
*phydev
)
330 mx6_rgmii_rework(phydev
);
332 if (phydev
->drv
->config
)
333 phydev
->drv
->config(phydev
);
338 #if defined(CONFIG_VIDEO_IPUV3)
339 static iomux_v3_cfg_t
const backlight_pads
[] = {
340 /* Power for LVDS Display */
341 MX6_PAD_EIM_D22__GPIO3_IO22
| MUX_PAD_CTRL(NO_PAD_CTRL
),
342 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
343 /* Backlight enable for LVDS display */
344 MX6_PAD_GPIO_0__GPIO1_IO00
| MUX_PAD_CTRL(NO_PAD_CTRL
),
345 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
346 /* backlight PWM brightness control */
347 MX6_PAD_SD1_DAT3__PWM1_OUT
| MUX_PAD_CTRL(NO_PAD_CTRL
),
350 static void do_enable_hdmi(struct display_info_t
const *dev
)
352 imx_enable_hdmi_phy();
355 int board_cfb_skip(void)
357 gpio_direction_output(LVDS_POWER_GP
, 1);
362 static int detect_baseboard(struct display_info_t
const *dev
)
364 if (IS_ENABLED(CONFIG_TARGET_GE_B450V3
) ||
365 IS_ENABLED(CONFIG_TARGET_GE_B650V3
))
371 struct display_info_t
const displays
[] = {{
374 .pixfmt
= IPU_PIX_FMT_RGB24
,
375 .detect
= detect_baseboard
,
378 .name
= "G121X1-L03",
390 .vmode
= FB_VMODE_NONINTERLACED
394 .pixfmt
= IPU_PIX_FMT_RGB24
,
395 .detect
= detect_hdmi
,
396 .enable
= do_enable_hdmi
,
410 .vmode
= FB_VMODE_NONINTERLACED
412 size_t display_count
= ARRAY_SIZE(displays
);
414 static void enable_videopll(void)
416 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
417 s32 timeout
= 100000;
419 setbits_le32(&ccm
->analog_pll_video
, BM_ANADIG_PLL_VIDEO_POWERDOWN
);
421 /* set video pll to 910MHz (24MHz * (37+11/12))
422 * video pll post div to 910/4 = 227.5MHz
424 clrsetbits_le32(&ccm
->analog_pll_video
,
425 BM_ANADIG_PLL_VIDEO_DIV_SELECT
|
426 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
,
427 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
428 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
430 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm
->analog_pll_video_num
);
431 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm
->analog_pll_video_denom
);
433 clrbits_le32(&ccm
->analog_pll_video
, BM_ANADIG_PLL_VIDEO_POWERDOWN
);
436 if (readl(&ccm
->analog_pll_video
) & BM_ANADIG_PLL_VIDEO_LOCK
)
440 printf("Warning: video pll lock timeout!\n");
442 clrsetbits_le32(&ccm
->analog_pll_video
,
443 BM_ANADIG_PLL_VIDEO_BYPASS
,
444 BM_ANADIG_PLL_VIDEO_ENABLE
);
447 static void setup_display_b850v3(void)
449 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
450 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
454 /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
455 clrbits_le32(&mxc_ccm
->cscmr2
, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV
);
459 /* Set LDB_DI0 as clock source for IPU_DI0 */
460 clrsetbits_le32(&mxc_ccm
->chsccdr
,
461 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK
,
462 (CHSCCDR_CLK_SEL_LDB_DI0
<<
463 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
));
465 /* Turn on IPU LDB DI0 clocks */
466 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_LDB_DI0_MASK
);
470 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
471 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
|
472 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
473 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|
474 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
|
475 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
476 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
|
477 IOMUXC_GPR2_SPLIT_MODE_EN_MASK
|
478 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
|
479 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
,
482 clrbits_le32(&iomux
->gpr
[3],
483 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
|
484 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
|
485 IOMUXC_GPR3_HDMI_MUX_CTL_MASK
);
488 static void setup_display_bx50v3(void)
490 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
491 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
493 /* When a reset/reboot is performed the display power needs to be turned
494 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
495 * an additional 200ms here. Unfortunately we use external PMIC for
496 * doing the reset, so can not differentiate between POR vs soft reset
500 /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
501 setbits_le32(&mxc_ccm
->cscmr2
, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV
);
503 /* Set LDB_DI0 as clock source for IPU_DI0 */
504 clrsetbits_le32(&mxc_ccm
->chsccdr
,
505 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK
,
506 (CHSCCDR_CLK_SEL_LDB_DI0
<<
507 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
));
509 /* Turn on IPU LDB DI0 clocks */
510 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_LDB_DI0_MASK
);
514 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
515 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
516 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
517 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
|
518 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
,
521 clrsetbits_le32(&iomux
->gpr
[3],
522 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
,
523 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<
524 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET
));
526 /* backlights off until needed */
527 imx_iomux_v3_setup_multiple_pads(backlight_pads
,
528 ARRAY_SIZE(backlight_pads
));
529 gpio_direction_input(LVDS_POWER_GP
);
530 gpio_direction_input(LVDS_BACKLIGHT_GP
);
532 #endif /* CONFIG_VIDEO_IPUV3 */
535 * Do not overwrite the console
536 * Use always serial for U-Boot console
538 int overwrite_console(void)
543 #define VPD_TYPE_INVALID 0x00
544 #define VPD_BLOCK_NETWORK 0x20
545 #define VPD_BLOCK_HWID 0x44
546 #define VPD_PRODUCT_B850 1
547 #define VPD_PRODUCT_B650 2
548 #define VPD_PRODUCT_B450 3
553 unsigned char mac1
[6];
557 * Extracts MAC and product information from the VPD.
559 static int vpd_callback(
567 struct vpd_cache
*vpd
= (struct vpd_cache
*)userdata
;
569 if ( id
== VPD_BLOCK_HWID
571 && type
!= VPD_TYPE_INVALID
573 vpd
->product_id
= data
[0];
575 } else if ( id
== VPD_BLOCK_NETWORK
577 && type
!= VPD_TYPE_INVALID
580 memcpy(vpd
->mac1
, data
, 6);
586 static void set_eth0_mac_address(unsigned char * mac
)
588 uint32_t *ENET_TCR
= (uint32_t*)0x21880c4;
589 uint32_t *ENET_PALR
= (uint32_t*)0x21880e4;
590 uint32_t *ENET_PAUR
= (uint32_t*)0x21880e8;
592 *ENET_TCR
|= 0x100; /* ADDINS */
593 *ENET_PALR
|= (mac
[0] << 24) | (mac
[1] << 16) | (mac
[2] << 8) | mac
[3];
594 *ENET_PAUR
|= (mac
[4] << 24) | (mac
[5] << 16);
597 static void process_vpd(struct vpd_cache
*vpd
)
599 if ( vpd
->product_id
== VPD_PRODUCT_B850
600 || vpd
->product_id
== VPD_PRODUCT_B650
601 || vpd
->product_id
== VPD_PRODUCT_B450
) {
602 if (vpd
->macbits
& 1) {
603 set_eth0_mac_address(vpd
->mac1
);
608 static int read_vpd(uint eeprom_bus
)
610 struct vpd_cache vpd
;
614 unsigned int current_i2c_bus
= i2c_get_bus_num();
616 res
= i2c_set_bus_num(eeprom_bus
);
620 data
= (uint8_t *)malloc(size
);
624 res
= i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR
, 0,
625 CONFIG_SYS_I2C_EEPROM_ADDR_LEN
, data
, size
);
628 memset(&vpd
, 0, sizeof(vpd
));
629 vpd_reader(size
, data
, &vpd
, vpd_callback
);
635 i2c_set_bus_num(current_i2c_bus
);
639 int board_eth_init(bd_t
*bis
)
644 return cpu_eth_init(bis
);
647 static iomux_v3_cfg_t
const misc_pads
[] = {
648 MX6_PAD_KEY_ROW2__GPIO4_IO11
| MUX_PAD_CTRL(NO_PAD_CTRL
),
649 MX6_PAD_EIM_A25__GPIO5_IO02
| MUX_PAD_CTRL(NC_PAD_CTRL
),
650 MX6_PAD_EIM_CS0__GPIO2_IO23
| MUX_PAD_CTRL(NC_PAD_CTRL
),
651 MX6_PAD_EIM_CS1__GPIO2_IO24
| MUX_PAD_CTRL(NC_PAD_CTRL
),
652 MX6_PAD_EIM_OE__GPIO2_IO25
| MUX_PAD_CTRL(NC_PAD_CTRL
),
653 MX6_PAD_EIM_BCLK__GPIO6_IO31
| MUX_PAD_CTRL(NC_PAD_CTRL
),
654 MX6_PAD_GPIO_1__GPIO1_IO01
| MUX_PAD_CTRL(NC_PAD_CTRL
),
656 #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
657 #define WIFI_EN IMX_GPIO_NR(6, 14)
659 int board_early_init_f(void)
661 imx_iomux_v3_setup_multiple_pads(misc_pads
,
662 ARRAY_SIZE(misc_pads
));
666 #if defined(CONFIG_VIDEO_IPUV3)
667 if (IS_ENABLED(CONFIG_TARGET_GE_B850V3
))
668 /* Set LDB clock to Video PLL */
669 select_ldb_di_clock_source(MXC_PLL5_CLK
);
671 /* Set LDB clock to USB PLL */
672 select_ldb_di_clock_source(MXC_PLL3_SW_CLK
);
679 gpio_direction_output(SUS_S3_OUT
, 1);
680 gpio_direction_output(WIFI_EN
, 1);
681 #if defined(CONFIG_VIDEO_IPUV3)
682 if (IS_ENABLED(CONFIG_TARGET_GE_B850V3
))
683 setup_display_b850v3();
685 setup_display_bx50v3();
687 /* address of boot parameters */
688 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
690 #ifdef CONFIG_MXC_SPI
693 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info1
);
694 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info2
);
695 setup_i2c(3, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info3
);
697 read_vpd(CONFIG_SYS_I2C_EEPROM_BUS
);
702 #ifdef CONFIG_CMD_BMODE
703 static const struct boot_mode board_boot_modes
[] = {
704 /* 4 bit bus width */
705 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
706 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
714 #define DA9063_I2C_ADDR 0x58
715 #define DA9063_REG_BCORE2_CFG 0x9D
716 #define DA9063_REG_BCORE1_CFG 0x9E
717 #define DA9063_REG_BPRO_CFG 0x9F
718 #define DA9063_REG_BIO_CFG 0xA0
719 #define DA9063_REG_BMEM_CFG 0xA1
720 #define DA9063_REG_BPERI_CFG 0xA2
721 #define DA9063_BUCK_MODE_MASK 0xC0
722 #define DA9063_BUCK_MODE_MANUAL 0x00
723 #define DA9063_BUCK_MODE_SLEEP 0x40
724 #define DA9063_BUCK_MODE_SYNC 0x80
725 #define DA9063_BUCK_MODE_AUTO 0xC0
729 i2c_set_bus_num(I2C_PMIC
);
731 i2c_read(DA9063_I2C_ADDR
, DA9063_REG_BCORE2_CFG
, 1, &val
, 1);
732 val
&= ~DA9063_BUCK_MODE_MASK
;
733 val
|= DA9063_BUCK_MODE_SYNC
;
734 i2c_write(DA9063_I2C_ADDR
, DA9063_REG_BCORE2_CFG
, 1, &val
, 1);
736 i2c_read(DA9063_I2C_ADDR
, DA9063_REG_BCORE1_CFG
, 1, &val
, 1);
737 val
&= ~DA9063_BUCK_MODE_MASK
;
738 val
|= DA9063_BUCK_MODE_SYNC
;
739 i2c_write(DA9063_I2C_ADDR
, DA9063_REG_BCORE1_CFG
, 1, &val
, 1);
741 i2c_read(DA9063_I2C_ADDR
, DA9063_REG_BPRO_CFG
, 1, &val
, 1);
742 val
&= ~DA9063_BUCK_MODE_MASK
;
743 val
|= DA9063_BUCK_MODE_SYNC
;
744 i2c_write(DA9063_I2C_ADDR
, DA9063_REG_BPRO_CFG
, 1, &val
, 1);
746 i2c_read(DA9063_I2C_ADDR
, DA9063_REG_BIO_CFG
, 1, &val
, 1);
747 val
&= ~DA9063_BUCK_MODE_MASK
;
748 val
|= DA9063_BUCK_MODE_SYNC
;
749 i2c_write(DA9063_I2C_ADDR
, DA9063_REG_BIO_CFG
, 1, &val
, 1);
751 i2c_read(DA9063_I2C_ADDR
, DA9063_REG_BMEM_CFG
, 1, &val
, 1);
752 val
&= ~DA9063_BUCK_MODE_MASK
;
753 val
|= DA9063_BUCK_MODE_SYNC
;
754 i2c_write(DA9063_I2C_ADDR
, DA9063_REG_BMEM_CFG
, 1, &val
, 1);
756 i2c_read(DA9063_I2C_ADDR
, DA9063_REG_BPERI_CFG
, 1, &val
, 1);
757 val
&= ~DA9063_BUCK_MODE_MASK
;
758 val
|= DA9063_BUCK_MODE_SYNC
;
759 i2c_write(DA9063_I2C_ADDR
, DA9063_REG_BPERI_CFG
, 1, &val
, 1);
762 int board_late_init(void)
764 #ifdef CONFIG_CMD_BMODE
765 add_board_boot_modes(board_boot_modes
);
768 #ifdef CONFIG_VIDEO_IPUV3
769 /* We need at least 200ms between power on and backlight on
770 * as per specifications from CHI MEI */
773 /* enable backlight PWM 1 */
776 /* duty cycle 5000000ns, period: 5000000ns */
777 pwm_config(0, 5000000, 5000000);
779 /* Backlight Power */
780 gpio_direction_output(LVDS_BACKLIGHT_GP
, 1);
785 /* board specific pmic init */
793 printf("BOARD: %s\n", CONFIG_BOARD_NAME
);