board/genesi/mx51_efikamx/imximage_mx.cfg

   1 /*
   2  * Copyright (C) 2009 Pegatron Corporation
   3  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   4  * Copyright (C) 2009-2012 Genesi USA, Inc.
   5  *
   6  * BASED ON: imx51evk
   7  *
   8  * (C) Copyright 2009
   9  * Stefano Babic DENX Software Engineering sbabic@denx.de.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  *
  13  * Refer doc/README.imximage for more details about how-to configure
  14  * and create imximage boot image
  15  *
  16  * The syntax is taken as close as possible with the kwbimage
  17  */
  18
  19 /*
  20  * Boot Device : one of
  21  * spi, sd (the board has no nand neither onenand)
  22  */
  23 BOOT_FROM       spi
  24
  25 /*
  26  * Device Configuration Data (DCD)
  27  *
  28  * Each entry must have the format:
  29  * Addr-type           Address        Value
  30  *
  31  * where:
  32  *      Addr-type register length (1,2 or 4 bytes)
  33  *      Address   absolute address of the register
  34  *      value     value to be stored in the register
  35  */
  36 /*
  37  * Essential GPIO settings to be done as early as possible
  38  * PCBIDn pad settings are all the defaults except #2 which needs HVE off
  39  */
  40 DATA 4 0x73fa8134 0x3                   # PCBID0 ALT3 GPIO 3_16
  41 DATA 4 0x73fa8130 0x3                   # PCBID1 ALT3 GPIO 3_17
  42 DATA 4 0x73fa8128 0x3                   # PCBID2 ALT3 GPIO 3_11
  43 DATA 4 0x73fa8504 0xe4                  # PCBID2 PAD ~HVE
  44 DATA 4 0x73fa8198 0x3                   # LED0 ALT3 GPIO 3_13
  45 DATA 4 0x73fa81c4 0x3                   # LED1 ALT3 GPIO 3_14
  46 DATA 4 0x73fa81c8 0x3                   # LED2 ALT3 GPIO 3_15
  47
  48 /* DDR bus IOMUX PAD settings */
  49 DATA 4 0x73fa850c 0x20c5                # SDODT1
  50 DATA 4 0x73fa8510 0x20c5                # SDODT0
  51 DATA 4 0x73fa84ac 0xc5                  # SDWE
  52 DATA 4 0x73fa84b0 0xc5                  # SDCKE0
  53 DATA 4 0x73fa84b4 0xc5                  # SDCKE1
  54 DATA 4 0x73fa84cc 0xc5                  # DRAM_CS0
  55 DATA 4 0x73fa84d0 0xc5                  # DRAM_CS1
  56 DATA 4 0x73fa882c 0x2                   # DRAM_B4
  57 DATA 4 0x73fa88a4 0x2                   # DRAM_B0
  58 DATA 4 0x73fa88ac 0x2                   # DRAM_B1
  59 DATA 4 0x73fa88b8 0x2                   # DRAM_B2
  60 DATA 4 0x73fa84d4 0xc5                  # DRAM_DQM0
  61 DATA 4 0x73fa84d8 0xc5                  # DRAM_DQM1
  62 DATA 4 0x73fa84dc 0xc5                  # DRAM_DQM2
  63 DATA 4 0x73fa84e0 0xc5                  # DRAM_DQM3
  64
  65 /*
  66  * Setting DDR for micron
  67  * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
  68  * CAS=3 BL=4
  69  */
  70 /* ESDCTL_ESDCTL0 */
  71 DATA 4 0x83fd9000 0x82a20000
  72 /* ESDCTL_ESDCTL1 */
  73 DATA 4 0x83fd9008 0x82a20000
  74 /* ESDCTL_ESDMISC */
  75 DATA 4 0x83fd9010 0xcaaaf6d0
  76 /* ESDCTL_ESDCFG0 */
  77 DATA 4 0x83fd9004 0x3f3574aa
  78 /* ESDCTL_ESDCFG1 */
  79 DATA 4 0x83fd900c 0x3f3574aa
  80
  81 /* Init DRAM on CS0 */
  82 /* ESDCTL_ESDSCR */
  83 DATA 4 0x83fd9014 0x04008008
  84 DATA 4 0x83fd9014 0x0000801a
  85 DATA 4 0x83fd9014 0x0000801b
  86 DATA 4 0x83fd9014 0x00448019
  87 DATA 4 0x83fd9014 0x07328018
  88 DATA 4 0x83fd9014 0x04008008
  89 DATA 4 0x83fd9014 0x00008010
  90 DATA 4 0x83fd9014 0x00008010
  91 DATA 4 0x83fd9014 0x06328018
  92 DATA 4 0x83fd9014 0x03808019
  93 DATA 4 0x83fd9014 0x00408019
  94 DATA 4 0x83fd9014 0x00008000
  95
  96 /* Init DRAM on CS1 */
  97 DATA 4 0x83fd9014 0x0400800c
  98 DATA 4 0x83fd9014 0x0000801e
  99 DATA 4 0x83fd9014 0x0000801f
 100 DATA 4 0x83fd9014 0x0000801d
 101 DATA 4 0x83fd9014 0x0732801c
 102 DATA 4 0x83fd9014 0x0400800c
 103 DATA 4 0x83fd9014 0x00008014
 104 DATA 4 0x83fd9014 0x00008014
 105 DATA 4 0x83fd9014 0x0632801c
 106 DATA 4 0x83fd9014 0x0380801d
 107 DATA 4 0x83fd9014 0x0040801d
 108 DATA 4 0x83fd9014 0x00008004
 109
 110 /* Write to CTL0 */
 111 DATA 4 0x83fd9000 0xb2a20000
 112 /* Write to CTL1 */
 113 DATA 4 0x83fd9008 0xb2a20000
 114 /* ESDMISC */
 115 DATA 4 0x83fd9010 0x000ad6d0
 116 /* ESDCTL_ESDCDLYGD */
 117 DATA 4 0x83fd9034 0x90000000
 118 DATA 4 0x83fd9014 0x00000000