board/gth2/lowlevel_init.S

   1 /* Memory sub-system initialization code */
   2
   3 #include <config.h>
   4 #include <asm/regdef.h>
   5 #include <asm/au1x00.h>
   6 #include <asm/mipsregs.h>
   7
   8 #define CP0_Config0             $16
   9 #define MEM_1MS                 ((CONFIG_SYS_MHZ) * 1000)
  10 #define GPIO_RJ1LY     (1<<22)
  11 #define GPIO_CFRESET   (1<<10)
  12
  13         .text
  14         .set noreorder
  15         .set mips32
  16
  17         .globl  lowlevel_init
  18 lowlevel_init:
  19         /*
  20          * Step 2) Establish Status Register
  21          * (set BEV, clear ERL, clear EXL, clear IE)
  22          */
  23         li      t1, 0x00400000
  24         mtc0    t1, CP0_STATUS
  25
  26         /*
  27          * Step 3) Establish CP0 Config0
  28          * (set OD, set K0=3)
  29          */
  30         li      t1, 0x00080003
  31         mtc0    t1, CP0_CONFIG
  32
  33         /*
  34          * Step 4) Disable Watchpoint facilities
  35          */
  36         li t1, 0x00000000
  37         mtc0    t1, CP0_WATCHLO
  38         mtc0    t1, CP0_IWATCHLO
  39         /*
  40          * Step 5) Disable the performance counters
  41          */
  42         mtc0    zero, CP0_PERFORMANCE
  43         nop
  44
  45         /*
  46          * Step 6) Establish EJTAG Debug register
  47          */
  48         mtc0    zero, CP0_DEBUG
  49         nop
  50
  51         /*
  52          * Step 7) Establish Cause
  53          * (set IV bit)
  54          */
  55         li      t1, 0x00800000
  56         mtc0    t1, CP0_CAUSE
  57
  58         /* Establish Wired (and Random) */
  59         mtc0    zero, CP0_WIRED
  60         nop
  61
  62         /* No workaround if running from ram */
  63         lui     t0, 0xffc0
  64         lui     t3, 0xbfc0
  65         and     t1, ra, t0
  66         bne     t1, t3, noCacheJump
  67         nop
  68
  69         /*** From AMD YAMON ***/
  70         /*
  71          * Step 8) Initialize the caches
  72          */
  73         li              t0, (16*1024)
  74         li              t1, 32
  75         li              t2, 0x80000000
  76         addu    t3, t0, t2
  77 cacheloop:
  78         cache   0, 0(t2)
  79         cache   1, 0(t2)
  80         addu    t2, t1
  81         bne             t2, t3, cacheloop
  82         nop
  83
  84         /* Save return address */
  85         move            t3, ra
  86
  87         /* Run from cacheable space now */
  88         bal             cachehere
  89         nop
  90 cachehere:
  91         li              t1, ~0x20000000 /* convert to KSEG0 */
  92         and             t0, ra, t1
  93         addi    t0, 5*4                 /* 5 insns beyond cachehere */
  94         jr              t0
  95         nop
  96
  97         /* Restore return address */
  98         move            ra, t3
  99
 100         /*
 101          * Step 9) Initialize the TLB
 102          */
 103         li              t0, 0                   # index value
 104         li              t1, 0x00000000          # entryhi value
 105         li              t2, 32                  # 32 entries
 106
 107 tlbloop:
 108         /* Probe TLB for matching EntryHi */
 109         mtc0    t1, CP0_ENTRYHI
 110         tlbp
 111         nop
 112
 113         /* Examine Index[P], 1=no matching entry */
 114         mfc0    t3, CP0_INDEX
 115         li      t4, 0x80000000
 116         and     t3, t4, t3
 117         addiu   t1, t1, 1               # increment t1 (asid)
 118         beq     zero, t3, tlbloop
 119         nop
 120
 121         /* Initialize the TLB entry */
 122         mtc0    t0, CP0_INDEX
 123         mtc0    zero, CP0_ENTRYLO0
 124         mtc0    zero, CP0_ENTRYLO1
 125         mtc0    zero, CP0_PAGEMASK
 126         tlbwi
 127
 128         /* Do it again */
 129         addiu   t0, t0, 1
 130         bne     t0, t2, tlbloop
 131         nop
 132
 133         /* First setup pll:s to make serial work ok */
 134         /* We have a 12.5 MHz crystal */
 135         li      t0, SYS_CPUPLL
 136         li      t1, 0x28  /* CPU clock, 500 MHz */
 137         sw      t1, 0(t0)
 138         sync
 139         nop
 140         nop
 141
 142         /* wait 1mS for clocks to settle */
 143         li      t1, MEM_1MS
 144 1:      add     t1, -1
 145         bne     t1, zero, 1b
 146         nop
 147         /* Setup AUX PLL */
 148         li      t0, SYS_AUXPLL
 149         li      t1, 0
 150         sw      t1, 0(t0) /* aux pll */
 151         sync
 152
 153         /*  Static memory controller */
 154         /* RCE0 - can not change while fetching, do so from icache */
 155         move            t2, ra /* Store return address */
 156         bal             getAddr
 157         nop
 158
 159 getAddr:
 160         move            t1, ra
 161         move            ra, t2 /* Move return addess back */
 162
 163         cache   0x14,0(t1)
 164         cache   0x14,32(t1)
 165         /*** /From YAMON ***/
 166
 167 noCacheJump:
 168
 169         /*  Static memory controller */
 170
 171         /* RCE0 AMD 29LV800 Flash */
 172         li      t0, MEM_STCFG0
 173         li      t1, 0x00000243
 174         sw      t1, 0(t0)
 175
 176         li      t0, MEM_STTIME0
 177         li      t1, 0x040181D7 /* FIXME */
 178         sw      t1, 0(t0)
 179
 180         li      t0, MEM_STADDR0
 181         li      t1, 0x11E03F80
 182         sw      t1, 0(t0)
 183
 184         /* RCE1 PCMCIA 250ns */
 185         li      t0, MEM_STCFG1
 186         li      t1, 0x00000002
 187         sw      t1, 0(t0)
 188
 189         li      t0, MEM_STTIME1
 190         li      t1, 0x280E3E07
 191         sw      t1, 0(t0)
 192
 193         li      t0, MEM_STADDR1
 194         li      t1, 0x10000000
 195         sw      t1, 0(t0)
 196
 197         /* RCE2 CP Altera */
 198         li      t0, MEM_STCFG2
 199         li      t1, 0x00000280 /* BE, EW */
 200         sw      t1, 0(t0)
 201
 202         li      t0, MEM_STTIME2
 203         li      t1, 0x0303000c
 204         sw      t1, 0(t0)
 205
 206         li      t0, MEM_STADDR2
 207         li      t1, 0x10c03f80 /* 1 MB */
 208         sw      t1, 0(t0)
 209
 210         /* RCE3 DP Altera */
 211         li      t0, MEM_STCFG3
 212         li      t1, 0x00000280 /* BE, EW */
 213         sw      t1, 0(t0)
 214
 215         li      t0, MEM_STTIME3
 216         li      t1, 0x0303000c
 217         sw      t1, 0(t0)
 218
 219         li      t0, MEM_STADDR3
 220         li      t1, 0x10e03f80 /* 1 MB */
 221         sw      t1, 0(t0)
 222
 223         sync
 224
 225         /* Set peripherals to a known state */
 226         li      t0, IC0_CFG0CLR
 227         li      t1, 0xFFFFFFFF
 228         sw      t1, 0(t0)
 229
 230         li      t0, IC0_CFG0CLR
 231         sw      t1, 0(t0)
 232
 233         li      t0, IC0_CFG1CLR
 234         sw      t1, 0(t0)
 235
 236         li      t0, IC0_CFG2CLR
 237         sw      t1, 0(t0)
 238
 239         li      t0, IC0_SRCSET
 240         sw      t1, 0(t0)
 241
 242         li      t0, IC0_ASSIGNSET
 243         sw      t1, 0(t0)
 244
 245         li      t0, IC0_WAKECLR
 246         sw      t1, 0(t0)
 247
 248         li      t0, IC0_RISINGCLR
 249         sw      t1, 0(t0)
 250
 251         li      t0, IC0_FALLINGCLR
 252         sw      t1, 0(t0)
 253
 254         li      t0, IC0_TESTBIT
 255         li      t1, 0x00000000
 256         sw      t1, 0(t0)
 257         sync
 258
 259         li      t0, IC1_CFG0CLR
 260         li      t1, 0xFFFFFFFF
 261         sw      t1, 0(t0)
 262
 263         li      t0, IC1_CFG0CLR
 264         sw      t1, 0(t0)
 265
 266         li      t0, IC1_CFG1CLR
 267         sw      t1, 0(t0)
 268
 269         li      t0, IC1_CFG2CLR
 270         sw      t1, 0(t0)
 271
 272         li      t0, IC1_SRCSET
 273         sw      t1, 0(t0)
 274
 275         li      t0, IC1_ASSIGNSET
 276         sw      t1, 0(t0)
 277
 278         li      t0, IC1_WAKECLR
 279         sw      t1, 0(t0)
 280
 281         li      t0, IC1_RISINGCLR
 282         sw      t1, 0(t0)
 283
 284         li      t0, IC1_FALLINGCLR
 285         sw      t1, 0(t0)
 286
 287         li      t0, IC1_TESTBIT
 288         li      t1, 0x00000000
 289         sw      t1, 0(t0)
 290         sync
 291
 292         li      t0, SYS_FREQCTRL0
 293         li      t1, 0x00000000
 294         sw      t1, 0(t0)
 295
 296         li      t0, SYS_FREQCTRL1
 297         li      t1, 0x00000000
 298         sw      t1, 0(t0)
 299
 300         li      t0, SYS_CLKSRC
 301         li      t1, 0x00000000
 302         sw      t1, 0(t0)
 303
 304         li      t0, SYS_PININPUTEN
 305         li      t1, 0x00000000
 306         sw      t1, 0(t0)
 307         sync
 308
 309         li      t0, 0xB1100100
 310         li      t1, 0x00000000
 311         sw      t1, 0(t0)
 312
 313         li      t0, 0xB1400100
 314         li      t1, 0x00000000
 315         sw      t1, 0(t0)
 316
 317
 318         li      t0, SYS_WAKEMSK
 319         li      t1, 0x00000000
 320         sw      t1, 0(t0)
 321
 322         li      t0, SYS_WAKESRC
 323         li      t1, 0x00000000
 324         sw      t1, 0(t0)
 325
 326         /* wait 1mS before setup */
 327         li      t1, MEM_1MS
 328 1:      add     t1, -1
 329         bne     t1, zero, 1b
 330         nop
 331
 332
 333 /* SDCS 0 SDRAM */
 334         li      t0, MEM_SDMODE0
 335         li      t1, 0x592CD1
 336         sw      t1, 0(t0)
 337
 338         li      t0, MEM_SDMODE1
 339         li      t1, 0x00000000
 340         sw      t1, 0(t0)
 341
 342         li      t0, MEM_SDMODE2
 343         li      t1, 0x00000000
 344         sw      t1, 0(t0)
 345
 346 /* 64 MB SDRAM at addr 0 */
 347         li      t0, MEM_SDADDR0
 348         li      t1, 0x001003F0
 349         sw      t1, 0(t0)
 350
 351
 352         li      t0, MEM_SDADDR1
 353         li      t1, 0x00000000
 354         sw      t1, 0(t0)
 355
 356         li      t0, MEM_SDADDR2
 357         li      t1, 0x00000000
 358         sw      t1, 0(t0)
 359
 360         sync
 361
 362         li      t0, MEM_SDREFCFG
 363         li      t1, 0x880007A1 /* Disable */
 364         sw      t1, 0(t0)
 365         sync
 366
 367         li      t0, MEM_SDPRECMD
 368         sw      zero, 0(t0)
 369         sync
 370
 371         li      t0, MEM_SDAUTOREF
 372         sw      zero, 0(t0)
 373         sync
 374         sw      zero, 0(t0)
 375         sync
 376
 377         li      t0, MEM_SDREFCFG
 378         li      t1, 0x8A0007A1 /* Enable */
 379         sw      t1, 0(t0)
 380         sync
 381
 382         li      t0, MEM_SDWRMD0
 383         li      t1, 0x00000023
 384         sw      t1, 0(t0)
 385         sync
 386
 387         /* wait 1mS after setup */
 388         li      t1, MEM_1MS
 389 1:      add     t1, -1
 390         bne     t1, zero, 1b
 391         nop
 392
 393         /* Setup GPIO pins */
 394
 395         li      t0, SYS_PINFUNC
 396         li      t1, 0x00007025 /* 0x8080 */
 397         sw      t1, 0(t0)
 398
 399         li      t0, SYS_TRIOUTCLR
 400         li      t1, 0xFFFFFFFF /* 0x1FFF */
 401         sw      t1, 0(t0)
 402
 403         /* Turn yellow front led on */
 404         /* Release reset on CF */
 405         li      t0, SYS_OUTPUTCLR
 406         li      t1, GPIO_RJ1LG
 407         sw      t1, 0(t0)
 408         li      t0, SYS_OUTPUTSET
 409         li      t1, GPIO_RJ1LY|GPIO_CFRESET
 410         sw      t1, 0(t0)
 411         sync
 412         j clearmem
 413         nop
 414
 415 #if 0
 416         .globl  memtest
 417 #endif
 418 memtest:
 419         /* Fill memory with address */
 420         li      t0, 0x80000000
 421         li      t1, 0xFFF000 /* 64 MB */
 422 mt0:    sw      t0, 0(t0)
 423         add     t1, -1
 424         add     t0, 4
 425         bne     t1, zero, mt0
 426         nop
 427         nop
 428         /* Verify addr */
 429         li      t0, 0x80000000
 430         li      t1, 0xFFF000 /* 64 MB */
 431 mt1:    lw      t2, 0(t0)
 432         bne     t0, t2, memhang
 433         add     t1, -1
 434         add     t0, 4
 435         bne     t1, zero, mt1
 436         nop
 437         nop
 438 #if 0
 439         .globl  clearmem
 440 #endif
 441 clearmem:
 442                 /* Clear memory */
 443         li      t0, 0x80000000
 444         li      t1, 0xFFF000 /* 64 MB */
 445 mtc:    sw      zero, 0(t0)
 446         add     t1, -1
 447         add     t0, 4
 448         bne     t1, zero, mtc
 449         nop
 450         nop
 451 memtestend:
 452         jr      ra
 453         nop
 454
 455 memhang:
 456         b       memhang
 457         nop