2 * (C) Copyright 2015 Linaro
3 * Peter Griffin <peter.griffin@linaro.org>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <dm/platform_data/serial_pl01x.h>
15 #include <power/hi6553_pmic.h>
16 #include <asm-generic/gpio.h>
17 #include <asm/arch/dwmmc.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/periph.h>
20 #include <asm/arch/pinmux.h>
21 #include <asm/arch/hi6220.h>
22 #include <asm/armv8/mmu.h>
24 /*TODO drop this table in favour of device tree */
25 static const struct hikey_gpio_platdata hi6220_gpio
[] = {
26 { 0, HI6220_GPIO_BASE(0)},
27 { 1, HI6220_GPIO_BASE(1)},
28 { 2, HI6220_GPIO_BASE(2)},
29 { 3, HI6220_GPIO_BASE(3)},
30 { 4, HI6220_GPIO_BASE(4)},
31 { 5, HI6220_GPIO_BASE(5)},
32 { 6, HI6220_GPIO_BASE(6)},
33 { 7, HI6220_GPIO_BASE(7)},
34 { 8, HI6220_GPIO_BASE(8)},
35 { 9, HI6220_GPIO_BASE(9)},
36 { 10, HI6220_GPIO_BASE(10)},
37 { 11, HI6220_GPIO_BASE(11)},
38 { 12, HI6220_GPIO_BASE(12)},
39 { 13, HI6220_GPIO_BASE(13)},
40 { 14, HI6220_GPIO_BASE(14)},
41 { 15, HI6220_GPIO_BASE(15)},
42 { 16, HI6220_GPIO_BASE(16)},
43 { 17, HI6220_GPIO_BASE(17)},
44 { 18, HI6220_GPIO_BASE(18)},
45 { 19, HI6220_GPIO_BASE(19)},
49 U_BOOT_DEVICES(hi6220_gpios
) = {
50 { "gpio_hi6220", &hi6220_gpio
[0] },
51 { "gpio_hi6220", &hi6220_gpio
[1] },
52 { "gpio_hi6220", &hi6220_gpio
[2] },
53 { "gpio_hi6220", &hi6220_gpio
[3] },
54 { "gpio_hi6220", &hi6220_gpio
[4] },
55 { "gpio_hi6220", &hi6220_gpio
[5] },
56 { "gpio_hi6220", &hi6220_gpio
[6] },
57 { "gpio_hi6220", &hi6220_gpio
[7] },
58 { "gpio_hi6220", &hi6220_gpio
[8] },
59 { "gpio_hi6220", &hi6220_gpio
[9] },
60 { "gpio_hi6220", &hi6220_gpio
[10] },
61 { "gpio_hi6220", &hi6220_gpio
[11] },
62 { "gpio_hi6220", &hi6220_gpio
[12] },
63 { "gpio_hi6220", &hi6220_gpio
[13] },
64 { "gpio_hi6220", &hi6220_gpio
[14] },
65 { "gpio_hi6220", &hi6220_gpio
[15] },
66 { "gpio_hi6220", &hi6220_gpio
[16] },
67 { "gpio_hi6220", &hi6220_gpio
[17] },
68 { "gpio_hi6220", &hi6220_gpio
[18] },
69 { "gpio_hi6220", &hi6220_gpio
[19] },
72 DECLARE_GLOBAL_DATA_PTR
;
74 #if !CONFIG_IS_ENABLED(OF_CONTROL)
76 static const struct pl01x_serial_platdata serial_platdata
= {
77 #if CONFIG_CONS_INDEX == 1
78 .base
= HI6220_UART0_BASE
,
79 #elif CONFIG_CONS_INDEX == 4
80 .base
= HI6220_UART3_BASE
,
82 #error "Unsupported console index value."
88 U_BOOT_DEVICE(hikey_seriala
) = {
89 .name
= "serial_pl01x",
90 .platdata
= &serial_platdata
,
94 static struct mm_region hikey_mem_map
[] = {
99 .attrs
= PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
100 PTE_BLOCK_INNER_SHARE
102 .virt
= 0x80000000UL
,
103 .phys
= 0x80000000UL
,
104 .size
= 0x80000000UL
,
105 .attrs
= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE
) |
106 PTE_BLOCK_NON_SHARE
|
107 PTE_BLOCK_PXN
| PTE_BLOCK_UXN
109 /* List terminator */
114 struct mm_region
*mem_map
= hikey_mem_map
;
116 #ifdef CONFIG_BOARD_EARLY_INIT_F
117 int board_uart_init(void)
119 switch (CONFIG_CONS_INDEX
) {
121 hi6220_pinmux_config(PERIPH_ID_UART0
);
124 hi6220_pinmux_config(PERIPH_ID_UART3
);
127 debug("%s: Unsupported UART selected\n", __func__
);
134 int board_early_init_f(void)
141 struct peri_sc_periph_regs
*peri_sc
=
142 (struct peri_sc_periph_regs
*)HI6220_PERI_BASE
;
144 struct alwayson_sc_regs
*ao_sc
=
145 (struct alwayson_sc_regs
*)ALWAYSON_CTRL_BASE
;
147 /* status offset from enable reg */
148 #define STAT_EN_OFF 0x2
150 void hi6220_clk_enable(u32 bitfield
, unsigned int *clk_base
)
154 data
= readl(clk_base
);
157 writel(bitfield
, clk_base
);
159 data
= readl(clk_base
+ STAT_EN_OFF
);
160 } while ((data
& bitfield
) == 0);
163 /* status offset from disable reg */
164 #define STAT_DIS_OFF 0x1
166 void hi6220_clk_disable(u32 bitfield
, unsigned int *clk_base
)
170 data
= readl(clk_base
);
173 writel(data
, clk_base
);
175 data
= readl(clk_base
+ STAT_DIS_OFF
);
176 } while (data
& bitfield
);
179 #define EYE_PATTERN 0x70533483
181 int board_usb_init(int index
, enum usb_init_type init
)
185 /* enable USB clock */
186 hi6220_clk_enable(PERI_CLK0_USBOTG
, &peri_sc
->clk0_en
);
188 /* take usb IPs out of reset */
189 writel(PERI_RST0_USBOTG_BUS
| PERI_RST0_POR_PICOPHY
|
190 PERI_RST0_USBOTG
| PERI_RST0_USBOTG_32K
,
193 data
= readl(&peri_sc
->rst0_stat
);
194 data
&= PERI_RST0_USBOTG_BUS
| PERI_RST0_POR_PICOPHY
|
195 PERI_RST0_USBOTG
| PERI_RST0_USBOTG_32K
;
199 data
= readl(&peri_sc
->ctrl5
);
200 data
&= ~PERI_CTRL5_PICOPHY_BC_MODE
;
201 data
|= PERI_CTRL5_USBOTG_RES_SEL
| PERI_CTRL5_PICOPHY_ACAENB
;
203 writel(data
, &peri_sc
->ctrl5
);
207 /* configure USB PHY */
208 data
= readl(&peri_sc
->ctrl4
);
210 /* make PHY out of low power mode */
211 data
&= ~PERI_CTRL4_PICO_SIDDQ
;
212 data
&= ~PERI_CTRL4_PICO_OGDISABLE
;
213 data
|= PERI_CTRL4_PICO_VBUSVLDEXTSEL
| PERI_CTRL4_PICO_VBUSVLDEXT
;
214 writel(data
, &peri_sc
->ctrl4
);
216 writel(EYE_PATTERN
, &peri_sc
->ctrl8
);
222 static int config_sd_carddetect(void)
226 /* configure GPIO8 as nopull */
227 writel(0, 0xf8001830);
229 gpio_request(8, "SD CD");
231 gpio_direction_input(8);
232 ret
= gpio_get_value(8);
235 printf("%s: SD card present\n", __func__
);
239 printf("%s: SD card not present\n", __func__
);
244 static void mmc1_init_pll(void)
248 /* select SYSPLL as the source of MMC1 */
249 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
250 writel(1 << 11 | 1 << 27, &peri_sc
->clk0_sel
);
252 data
= readl(&peri_sc
->clk0_sel
);
253 } while (!(data
& (1 << 11)));
255 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
256 writel(1 << 30, &peri_sc
->clk0_sel
);
258 data
= readl(&peri_sc
->clk0_sel
);
259 } while (data
& (1 << 14));
261 hi6220_clk_enable(PERI_CLK0_MMC1
, &peri_sc
->clk0_en
);
263 hi6220_clk_enable(PERI_CLK12_MMC1_SRC
, &peri_sc
->clk12_en
);
266 /* 1.2GHz / 50 = 24MHz */
267 writel(0x31 | (1 << 7), &peri_sc
->clkcfg8bit2
);
268 data
= readl(&peri_sc
->clkcfg8bit2
);
269 } while ((data
& 0x31) != 0x31);
272 static void mmc1_reset_clk(void)
276 /* disable mmc1 bus clock */
277 hi6220_clk_disable(PERI_CLK0_MMC1
, &peri_sc
->clk0_dis
);
279 /* enable mmc1 bus clock */
280 hi6220_clk_enable(PERI_CLK0_MMC1
, &peri_sc
->clk0_en
);
282 /* reset mmc1 clock domain */
283 writel(PERI_RST0_MMC1
, &peri_sc
->rst0_en
);
285 /* bypass mmc1 clock phase */
286 data
= readl(&peri_sc
->ctrl2
);
288 writel(data
, &peri_sc
->ctrl2
);
290 /* disable low power */
291 data
= readl(&peri_sc
->ctrl13
);
293 writel(data
, &peri_sc
->ctrl13
);
295 data
= readl(&peri_sc
->rst0_stat
);
296 } while (!(data
& PERI_RST0_MMC1
));
298 /* unreset mmc0 clock domain */
299 writel(PERI_RST0_MMC1
, &peri_sc
->rst0_dis
);
301 data
= readl(&peri_sc
->rst0_stat
);
302 } while (data
& PERI_RST0_MMC1
);
305 /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
306 static void hi6220_pmussi_init(void)
310 /* Take PMUSSI out of reset */
311 writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N
,
314 data
= readl(&ao_sc
->rst4_stat
);
315 } while (data
& ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N
);
317 /* set PMU SSI clock latency for read operation */
318 data
= readl(&ao_sc
->mcu_subsys_ctrl3
);
319 data
&= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK
;
320 data
|= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3
;
321 writel(data
, &ao_sc
->mcu_subsys_ctrl3
);
323 /* enable PMUSSI clock */
324 data
= ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU
|
325 ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU
;
327 hi6220_clk_enable(data
, &ao_sc
->clk5_en
);
329 /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
330 gpio_request(0, "PWR_HOLD_GPIO0_0");
331 gpio_direction_output(0, 1);
334 int misc_init_r(void)
346 static int init_dwmmc(void)
352 /* mmc0 clocks are already configured by ATF */
353 ret
= hi6220_pinmux_config(PERIPH_ID_SDMMC0
);
355 printf("%s: Error configuring pinmux for eMMC (%d)\n"
358 ret
|= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE
, 8);
360 printf("%s: Error adding eMMC port (%d)\n", __func__
, ret
);
363 /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
367 ret
|= hi6220_pinmux_config(PERIPH_ID_SDMMC1
);
369 printf("%s: Error configuring pinmux for eMMC (%d)\n"
372 config_sd_carddetect();
374 ret
|= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE
, 4);
376 printf("%s: Error adding SD port (%d)\n", __func__
, ret
);
382 /* setup board specific PMIC */
383 int power_init_board(void)
385 /* init the hi6220 pmussi ip */
386 hi6220_pmussi_init();
388 power_hi6553_init((u8
*)HI6220_PMUSSI_BASE
);
393 int board_mmc_init(bd_t
*bis
)
397 /* add the eMMC and sd ports */
401 debug("init_dwmmc failed\n");
409 gd
->ram_size
= PHYS_SDRAM_1_SIZE
;
413 int dram_init_banksize(void)
416 * Reserve regions below from DT memory node (which gets generated
417 * by U-Boot from the dram banks in arch_fixup_fdt() before booting
418 * the kernel. This will then match the kernel hikey dts memory node.
420 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
421 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
422 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
423 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
424 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
425 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
428 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
429 gd
->bd
->bi_dram
[0].size
= 0x05e00000;
431 gd
->bd
->bi_dram
[1].start
= 0x05f00000;
432 gd
->bd
->bi_dram
[1].size
= 0x00001000;
434 gd
->bd
->bi_dram
[2].start
= 0x05f02000;
435 gd
->bd
->bi_dram
[2].size
= 0x00efd000;
437 gd
->bd
->bi_dram
[3].start
= 0x06e00000;
438 gd
->bd
->bi_dram
[3].size
= 0x0060f000;
440 gd
->bd
->bi_dram
[4].start
= 0x07410000;
441 gd
->bd
->bi_dram
[4].size
= 0x1aaf0000;
443 gd
->bd
->bi_dram
[5].start
= 0x22000000;
444 gd
->bd
->bi_dram
[5].size
= 0x1c000000;
449 void reset_cpu(ulong addr
)
451 writel(0x48698284, &ao_sc
->stat0
);